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7810D-AVR-01/
Features
● High performance, low power AVR ®^ 8-bit microcontroller
● Advanced RISC architecture
● 131 powerful instructions – most single clock cycle execution ● 32 8 general purpose working registers ● Fully static operation ● Up to 16MIPS throughput at 16MHz ● On-chip 2-cycle multiplier
● High endurance non-volatile memory segments
● 32K bytes of in-system self-programmable flash program memory ● 1Kbytes EEPROM ● 2Kbytes internal SRAM ● Write/erase cycles: 10,000 flash/100,000 EEPROM ● Optional boot code section with independent lock bits ● In-system programming by on-chip boot program ● True read-while-write operation ● Programming lock for software security
● Peripheral features
● Two 8-bit Timer/Counters with separate prescaler and compare mode ● One 16-bit Timer/Counter with separate prescaler, compare mode, and capture mode ● Real time counter with separate oscillator ● Six PWM channels ● 8-channel 10-bit ADC in TQFP and QFN/MLF package ● Temperature measurement ● Programmable serial USART ● Master/slave SPI serial interface ● Byte-oriented 2-wire serial interface (Phillips I 2 C compatible) ● Programmable watchdog timer with separate on-chip oscillator ● On-chip analog comparator ● Interrupt and wake-up on pin change
● Special microcontroller features
● Power-on reset and programmable brown-out detection ● Internal calibrated oscillator ● External and internal interrupt sources ● Six sleep modes: Idle, ADC noise reduction, power-save, power-down, standby, and extended standby
ATmega328P
8-bit AVR Microcontroller with 32K Bytes In-System
Programmable Flash
DATASHEET
ATmega328P [DATASHEET]
● I/O and packages
● 23 programmable I/O lines ● 32-lead TQFP, and 32-pad QFN/MLF
● Operating voltage:
● 2.7V to 5.5V for ATmega328P
● Temperature range:
● Automotive temperature range: –40°C to +125°C
● Speed grade:
● 0 to 8MHz at 2.7 to 5.5V (automotive temperature range: –40°C to +125°C) ● 0 to 16MHz at 4.5 to 5.5V (automotive temperature range: –40°C to +125°C)
● Low power consumption
● Active mode: 1.5mA at 3V - 4MHz ● Power-down mode: 1μA at 3V
ATmega328P [DATASHEET]
1.1 Pin Descriptions
1.1.1 VCC
Digital supply voltage.
1.1.2 GND
Ground.
1.1.3 Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Depending on the clock selection fuse settings, PB6 can be used as input to the inverting oscillator amplifier and input to the internal clock operating circuit. Depending on the clock selection fuse settings, PB7 can be used as output from the inverting oscillator amplifier. If the internal calibrated RC oscillator is used as chip clock source, PB7..6 is used as TOSC2..1 input for the asynchronous Timer/Counter2 if the AS2 bit in ASSR is set. The various special features of port B are elaborated in Section 13.3.1 “Alternate Functions of Port B” on page 65 and Section 8. “System Clock and Clock Options” on page 24.
1.1.4 Port C (PC5:0)
Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The PC5..0 output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.
1.1.5 PC6/RESET
If the RSTDISBL fuse is programmed, PC6 is used as an input pin. If the RSTDISBL fuse is unprogrammed, PC6 is used as a reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 28-4 on page 261. Shorter pulses are not guaranteed to generate a reset. The various special features of port C are elaborated in Section 13.3.2 “Alternate Functions of Port C” on page 68.
1.1.6 Port D (PD7:0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, port D pins that are externally pulled low will source current if the pull-up resistors are activated. The port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. The various special features of port D are elaborated in Section 13.3.3 “Alternate Functions of Port D” on page 70.
1.1.7 AV CC
AVCC is the supply voltage pin for the A/D converter, PC3:0, and ADC7:6. It should be externally connected to VCC , even if the ADC is not used. If the ADC is used, it should be connected to V (^) CC through a low-pass filter. Note that PC6..4 use digital supply voltage, VCC.
1.1.8 AREF
AREF is the analog reference pin for the A/D converter.
ATmega328P [DATASHEET] 5
1.1.9 ADC7:6 (TQFP and QFN/MLF Package Only)
In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter. These pins are powered from the analog supply and serve as 10-bit ADC channels.
1.2 Disclaimer
Typical values contained in this datasheet are based on simulations and characterization of actual ATmega328P AVR ® microcontrollers manufactured on the typical process technology. automotive min and max values are based on characterization of actual ATmega328P AVR microcontrollers manufactured on the whole process excursion (corner run).
1.3 Automotive Quality Grade
The ATmega328P have been developed and manufactured according to the most stringent requirements of the international standard ISO-TS-16949. This data sheet contains limit values extracted from the results of extensive characterization (temperature and voltage). The quality and reliability of the ATmega328P have been verified during regular product qualification as per AEC-Q100 grade 1. As indicated in the ordering information paragraph, the products are available in only one temperature.
Table 1-1. Temperature Grade Identification for Automotive Products
Temperature Temperature Identifier Comments –40°C; +125°C Z Full automotive temperature range
ATmega328P [DATASHEET] 7
The AVR ®^ core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The Atmel®^ ATmega328P provides the following features: 32K bytes of in-system programmable flash with read-while-write capabilities, 1K bytes EEPROM, 2K bytes SRAM, 23 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, a byte- oriented 2-wire serial interface, an SPI serial port, a 6-channel 10-bit ADC (8 channels in TQFP and QFN/MLF packages), a programmable watchdog timer with internal oscillator, and five software selectable power saving modes. The idle mode stops the CPU while allowing the SRAM, Timer/Counters, USART, 2-wire serial interface, SPI port, and interrupt system to continue functioning. The power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. In power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC noise reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In standby mode, the crystal/resonator oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption.
The device is manufactured using Atmel high density non-volatile memory technology. The on-chip ISP flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional non-volatile memory programmer, or by an on-chip boot program running on the AVR core. The boot program can use any interface to download the application program in the application flash memory. Software in the boot flash section will continue to run while the application flash section is updated, providing true read-while-write operation. By combining an 8-bit RISC CPU with in-system self-programmable flash on a monolithic chip, the Atmel ATmega328P is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.
The ATmega328P AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
ATmega328P [DATASHEET]
3. Resources
A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.
4. Data Retention
Reliability qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.
5. About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
ATmega328P [DATASHEET]
The fast-access register file contains 32 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle arithmetic logic unit (ALU) operation. In a typical ALU operation, two operands are output from the register file, the operation is executed, and the result is stored back in the register file – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for data space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR ®^ instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. Program flash memory space is divided in two sections, the boot program section and the application program section. Both sections have dedicated lock bits for write and read/write protection. The SPM instruction that writes into the application flash memory section must reside in the boot program section. During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The stack pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All interrupts have a separate interrupt vector in the interrupt vector table. The interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as control registers, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the data space locations following those of the register file, 0x20 - 0x5F. In addition, the ATmega328P has extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.
6.2 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See Section “” on page 281 for a detailed description.
6.3 Status Register
The status register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software.
ATmega328P [DATASHEET] 11
6.3.1 SREG – AVR Status Register
The AVR status register – SREG – is defined as:
- Bit 7 – I: Global Interrupt Enable The global interrupt enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. - Bit 6 – T: Bit Copy Storage The bit copy instructions BLD (bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction. - Bit 5 – H: Half Carry Flag The half carry flag H indicates a half carry in some arithmetic operations. Half carry Is useful in BCD arithmetic. See Section “” on page 281 for detailed information. - Bit 4 – S: Sign Bit, S = N V The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See Section “” on page 281 for detailed information. - Bit 3 – V: Two’s Complement Overflow Flag The two’s complement overflow flag V supports two’s complement arithmetics. See Section “” on page 281 for detailed information. - Bit 2 – N: Negative Flag The negative flag N indicates a negative result in an arithmetic or logic operation. See Section “” on page 281 for detailed information. - Bit 1 – Z: Zero Flag The zero flag Z indicates a zero result in an arithmetic or logic operation. See Section “” on page 281 for detailed information. - Bit 0 – C: Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See Section “” on page 281 for detailed information.
Bit 7 6 5 4 3 2 1 0 0x3F (0x5F) I T H S V N Z C SREG Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0
ATmega328P [DATASHEET] 13
6.4.1 The X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 6-3.
Figure 6-3. The X-, Y-, and Z-registers
In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details).
6.5 Stack Pointer
The stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. Note that the stack is implemented as growing from higher to lower memory locations. The stack pointer register always points to the top of the stack. The stack pointer points to the data SRAM stack area where the subroutine and interrupt stacks are located. A stack PUSH command will decrease the stack pointer. The stack in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. initial stack pointer value equals the last address of the internal SRAM and the stack pointer must be set to point above start of the SRAM, see Figure 7-2 on page 18. See Table 6-1 for stack pointer details.
The AVR stack pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR ®^ architecture is so small that only SPL is needed. In this case, the SPH register will not be present.
15 XH XL 0 X-register 7 0 7 0 R27 (0x1B) R26 (0x1A)
15 YH YL 0 Y-register 7 0 7 0 R29 (0x1D) R28 (0x1C)
15 ZH ZL 0 Z-register 7 0 7 0 R31 (0x1F) R30 (0x1E)
Table 6-1. Stack Pointer instructions
Instruction Stack pointer Description PUSH Decremented by 1 Data is pushed onto the stack CALL ICALL RCALL
Decremented by 2 Return address is pushed onto the stack with a subroutine call or interrupt
POP Incremented by 1 Data is popped from the stack RET RETI Incremented by 2^
Return address is popped from the stack with return from subroutine or return from interrupt
ATmega328P [DATASHEET]
6.5.1 SPH and SPL – Stack Pointer High and Stack Pointer Low Register
6.6 Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR ®^ CPU is driven by the CPU clock clkCPU , directly generated from the selected clock source for the chip. No internal clock division is used. Figure 6-4 shows the parallel instruction fetches and instruction executions enabled by the harvard architecture and the fast-access register file concept. This is the basic pipelining concept to obtain up to 1MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.
Figure 6-4. The Parallel Instruction Fetches and Instruction Executions
Figure 6-5 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register.
Figure 6-5. Single Cycle ALU Operation
Bit 15 14 13 12 11 10 9 8 0x3E (0x5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH 0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 7 6 5 4 3 2 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
clk (^) CPU
1st Instruction Fetch
1st Instruction Execute 2nd Instruction Fetch
T1 T2 T3 T
2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch
clk (^) CPU
T
Register Operands Fetch
Result Write Back
ALU Operation Execute
Total Execution Time
T2 T3 T
ATmega328P [DATASHEET]
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.
6.7.1 Interrupt Response Time
The interrupt execution response for all the enabled AVR ®^ interrupts is four clock cycles minimum. After four clock cycles the program vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the program counter is pushed onto the stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the program counter (two bytes) is popped back from the stack, the stack pointer is incremented by two, and the I-bit in SREG is set.
Assembly Code Example
in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<<EEMPE); /* start EEPROM write */ EECR |= (1<<EEPE); SREG = cSREG; /* restore SREG value (I-bit) */
Assembly Code Example
sei ; set Global Interrupt Enable sleep ; enter sleep, waiting for interrupt ; note: will enter sleep before any pending interrupt(s)
C Code Example
__enable_interrupt(); /* set Global Interrupt Enable */ __sleep(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */
ATmega328P [DATASHEET] 17
7. AVR Memories
7.1 Overview
This section describes the different memories in the ATmega328P. The AVR®^ architecture has two main memory spaces, the data memory and the program memory space. In addition, the ATmega328P features an EEPROM memory for data storage. All three memory spaces are linear and regular.
7.2 In-System Reprogrammable Flash Program Memory
The ATmega328P contains 32Kbytes on-chip in-system reprogrammable flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the flash is organized as 16K 16. For software security, the flash program memory space is divided into two sections, boot loader section and application program section in ATmega328P. See SELFPRGEN description in Section 25.3.1 “SPMCSR – Store Program Memory Control and Status Register” on page 228 and Section 26.9.1 “SPMCSR – Store Program Memory Control and Status Register” on page 239 for more details. The flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega328P program counter (PC) is 14 bits wide, thus addressing the 16K program memory locations. The operation of boot program section and associated boot lock bits for software protection are described in detail in Section 25. “Self-Programming the Flash, ATmega328P” on page 223 and Section 26. “Boot Loader Support – Read-While-Write Self-Programming” on page 229. Section 27. “Memory Programming” on page 241 contains a detailed description on flash programming in SPI- or parallel programming mode. Constant tables can be allocated within the entire program memory address space (see the LPM – load program memory instruction description). Timing diagrams for instruction fetch and execution are presented in Section 6.6 “Instruction Execution Timing” on page 14.
Figure 7-1. Program Memory Map ATmega328P
0x
0x3FFF
Boot Flash Section
Program Memory
Application Flash Section
ATmega328P [DATASHEET] 19
7.4 EEPROM Data Memory
The Atmel ®^ ATmega328P contains 1Kbyte of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM address registers, the EEPROM data register, and the EEPROM control register. Section 27. “Memory Programming” on page 241 contains a detailed description on EEPROM programming in SPI or parallel programming mode.
7.4.1 EEPROM Read/Write Access
The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 7-2 on page 22. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V (^) CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See Section 7.4.2 “Preventing EEPROM Corruption” on page 19 for details on how to avoid problems in these situations. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM control register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.
7.4.2 Preventing EEPROM Corruption
During periods of low V (^) CC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low. EEPROM data corruption can easily be avoided by following this design recommendation: Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal brown-out detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low V (^) CC reset protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.
7.5 I/O Memory
The I/O space definition of the ATmega328P is shown in Section “” on page 275. All ATmega328P I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega328P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the IN and OUT instructions. For the extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVR ®, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. The I/O and peripherals control registers are explained in later sections.
ATmega328P [DATASHEET]
7.5.1 General Purpose I/O Registers
The Atmel ®^ ATmega328P contains three general purpose I/O registers. These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags. General purpose I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
7.6 Register Description
7.6.1 EEARH and EEARL – The EEPROM Address Register
- Bits 15..9 – Res: Reserved Bits These bits are reserved bits in the Atmel ATmega328P and will always read as zero. - Bits 8..0 – EEAR8..0: EEPROM Address The EEPROM address registers – EEARH and EEARL specify the EEPROM address in the 256/512/512/1K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 255/511/511/1023. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. EEAR8 is an unused bit in ATmega328P and must always be written to zero.
7.6.2 EEDR – The EEPROM Data Register
- Bits 7..0 – EEDR7.0: EEPROM Data For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.
7.6.3 EECR – The EEPROM Control Register
- Bits 7..6 – Res: Reserved Bits These bits are reserved bits in the Atmel ATmega328P and will always read as zero. - Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits The EEPROM programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the erase and write operations in two different operations. The programming times for the different modes are shown in Table 7-1. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.
Bit 15 14 13 12 11 10 9 8 0x22 (0x42) – – – – – – – EEAR8 EEARH 0x21 (0x41) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL 7 6 5 4 3 2 1 0 Read/Write R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 X X X X X X X X X
Bit 7 6 5 4 3 2 1 0 0x20 (0x40) MSB LSB EEDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0 0x1F (0x3F) – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 X X 0 0 X 0
