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Floating Point Multiplier Assignment: Testing and VHDL Implementation, Slides of Computer Science

Chaudhary Charan Singh Haryana Agricultural University Computer Science

Information on a university assignment for designing a floating point multiplier using vhdl. It includes details on the assignment requirements, input and output formats, special cases, and testing methods. Students are expected to write a vhdl process to perform the floating point multiplication and test the design using provided test vectors.

Typology: Slides

2012/2013

Uploaded on 03/22/2013

dhritiman 🇮🇳

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Lecture 6 - Writing Tests

•A difference if treating the design as a black

box or if you have access to internal signals

•EE762 assignment testbenches treat student

design as a black box

•Must know what you are testing

•Must test corner cases

Docsity.com

Partial preview of the text

Download Floating Point Multiplier Assignment: Testing and VHDL Implementation and more Slides Computer Science in PDF only on Docsity!

Lecture 6 - Writing Tests

• A difference if treating the design as a black

box or if you have access to internal signals

• EE762 assignment testbenches treat student

design as a black box

• Must know what you are testing

• Must test corner cases

Floating Point Multiplier

• Used as a EE762 assignment

Floating Point

M ultiplier

A B

C

latch

drive

Project Assignment #10 Floating Pt Unit DUE: Mon Mar 10

In this assignment you will use VHDL to describe the function of a floating point multiplier. The

multiplier will accept IEEE Standard 754 single precision inputs and produce single precision

output. It will support NaN, ±∞, ±0, normalized numbers, and denormalized numbers.

The interface to the design will be:

The Assignment (2)

fpm.do - do file for listing and waveform

Other NOTES for floating point multiplier.

The test bench also uses a concurrent procedure call that reads the testvector file in

~degroat/ee762_assign/fpmvectors. Use of these vectors is hard coded in the concurrent procedure as are the checks and

grading routine. This procedure has been compiled and is in the library assign in this directory. To provide the mapping to

it you must execute the unix command

qhmap assign /user2/faculty/degroat/ee762_assign/assign

This provides the logical mapping such that the library clause in the test bench know where library assign is located. This

must be done prior to compiling the test bench. The procedure will also do the grading of this assignment.

Floating Point Standard

Single Precision Floating Point Format

Value is

If e = 255 and f ≠ 0, then v is NaN regardless of s

If e = 255 and f = 0, then v = (-1)s ∞

If 0 < e < 255, then v = (-1)s 2e- 127 (1.f)

If e = 0 and f ≠ 0, then v = (-1)s 2- 126 (x.f)

(denormalized numbers)(x is msb of value stored)

If e = 0 and f = 0, then v = (-1)s 0 (zero)

s e (8 bits) f (23 bits)

What to Check

• How to test the floating point multiplier for

both timing of inputs and outputs and

functional operation?

• Assume you have no knowledge of how

design is going to be implemented

The Test Vectors

Must test for normal operation and boundary conditions

A input by B input

NaN NaN

±Denorm ±Denorm

±Norm ±Norm

Denorm * OtherVal = Max Denorm

Denorm * OtherVal = Min Norm

Rounding using first guard bit

Rounding using 1st and 2nd guart bits

The Inputs – Example
...NaN 01111111100000000000000000000001...NaN
...Nan
...NaN 01111111100000000000000000000001.+INIF
...Nan
...NaN 01111111100000000000000000000001.-INIF
...Nan
...NaN 01111111100000000000000000000001....+0
...Nan
...NaN 01111111100000000000000000000001....-0
...Nan
...NaN 01111111100000000000000000000001....+1
...Nan
...NaN 01111111100000000000000000000001....-1
...Nan
...NaN 01111111100000000000000000000001...+25
...Nan
...NaN 01111111100000000000000000000001...-25
...Nan
...NaN 01111111100000000000000000000001..+100
...Nan
...NaN 01111111100000000000000000000001.1/100
...Nan
...NaN 01111111100000000000000000000001+DNORM
...Nan
...NaN 01111111100000000000000000000001-DNORM
...Nan
.+INIF 01111111100000000000000000000000...NaN
...NaN
- The Inputs – Example
...+25 01000001110010000000000000000000....+0
....+0
...+25 01000001110010000000000000000000....-0
....-0
...+25 01000001110010000000000000000000....+1
...+25
...+25 01000001110010000000000000000000....-1
...-25
...+25 01000001110010000000000000000000...+25
..+625
...+25 01000001110010000000000000000000...-25
..-625
...+25 01000001110010000000000000000000..+100
.+2500
...+25 01000001110010000000000000000000.1/100
.+0.25
...+25 01000001110010000000000000000000+DNORM
small1
...+25 01000001110010000000000000000000-DNORM
small2
...-25 11000001110010000000000000000000...NaN
...NaN
...-25 11000001110010000000000000000000.+INIF
.-INIF
...-25 11000001110010000000000000000000.-INIF
.+INIF
...-25 11000001110010000000000000000000....+0
....-0

Applying Inputs to Design

Inputs are read

from a file and

applied to the

design

WHILE (NOT ENDFILE(test_data)) LOOP

--get next input test vector and expected result

readline(test_data,cur_line);

read(cur_line,aid); read(cur_line,a_test_val);

read(cur_line,bid); read(cur_line,b_test_val);

readline(test_data,cur_line);

read(cur_line,resid);read(cur_line,result_val);

std_result_val := To_StdLogicVector(result_val);

num_tests := num_tests + 1;

-- run through bus cycle to send data to unit

aid_sig <= "======", aid after 20 ns;

bid_sig <= "======", bid after 20 ns;

resid_sig <= "======", resid after 20 ns;

-- drive signals on bus

aval <= To_StdLogicVector(a_test_val) after 20 ns, HIGHZ after 80 ns;

bval <= To_StdLogicVector(b_test_val) after 20 ns, HIGHZ after 80 ns;

latch <= '0' after 20 ns, '1' after 70 ns;

wait for 100 ns;

drive <= '0' after 20 ns, '1' after 80 ns;

exp_res <= std_result_val after 20 ns, HIGHZ after 80 ns;

wait for 50 ns;

ASSERT (C = std_result_val)

REPORT "result does not agree with expected result"

SEVERITY WARNING;

IF (C /= std_result_val) THEN

num_errors := num_errors + 1;

err_sig <= '1', '0' after 10 ns;

END IF;

wait for 50 ns;

END LOOP;

File I/O

• And then must

also do the

declarations for

File I/O

• Note that the file

I/O here uses the

1987 version of

the language

library ieee; use ieee.std_logic_1164.all; use STD.TEXTIO.all; package fpm_test_vect is constant HIGHZ : std_logic_vector (31 downto 0) := "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; procedure gen_vec (SIGNAL aid_sig,bid_sig,resid_sig : OUT string (1 to 6); SIGNAL aval,bval,exp_res : OUT std_logic_vector ( downto 0); SIGNAL C : IN std_logic_vector (31 downto 0); SIGNAL latch,drive : OUT std_ulogic; SIGNAL err_sig : OUT bit; SIGNAL score : OUT integer); end fpm_test_vect; package body fpm_test_vect is procedure gen_vec (SIGNAL aid_sig,bid_sig,resid_sig : OUT string (1 to 6); SIGNAL aval,bval,exp_res : OUT std_logic_vector ( downto 0); SIGNAL C : IN std_logic_vector (31 downto 0); SIGNAL latch,drive : OUT std_ulogic; SIGNAL err_sig : OUT bit; SIGNAL score : OUT integer) is variable cur_line : LINE; file test_data: TEXT is IN "/rcc4/faculty/degroat/ee762_assign/fpmvectors"; variable a_test_val, b_test_val : bit_vector (31 downto 0); variable result_val : bit_vector (31 downto 0); variable std_result_val : std_logic_vector (31 downto 0); variable aid,bid,resid : string (1 to 6); variable num_tests,num_errors : integer := 0;

Floating Point Multiplier Assignment: Testing and VHDL Implementation, Slides of Computer Science

Related documents

Partial preview of the text

Download Floating Point Multiplier Assignment: Testing and VHDL Implementation and more Slides Computer Science in PDF only on Docsity!

Lecture 6 - Writing Tests

• A difference if treating the design as a black

box or if you have access to internal signals

• EE762 assignment testbenches treat student

design as a black box

• Must know what you are testing

• Must test corner cases

Floating Point Multiplier

• Used as a EE762 assignment

Floating Point

M ultiplier

A B

C

latch

drive

Project Assignment #10 Floating Pt Unit DUE: Mon Mar 10

In this assignment you will use VHDL to describe the function of a floating point multiplier. The

multiplier will accept IEEE Standard 754 single precision inputs and produce single precision

output. It will support NaN, ±∞, ±0, normalized numbers, and denormalized numbers.

The interface to the design will be:

The Assignment (2)

fpm.do - do file for listing and waveform

Other NOTES for floating point multiplier.

The test bench also uses a concurrent procedure call that reads the testvector file in

~degroat/ee762_assign/fpmvectors. Use of these vectors is hard coded in the concurrent procedure as are the checks and

grading routine. This procedure has been compiled and is in the library assign in this directory. To provide the mapping to

it you must execute the unix command

qhmap assign /user2/faculty/degroat/ee762_assign/assign

This provides the logical mapping such that the library clause in the test bench know where library assign is located. This

must be done prior to compiling the test bench. The procedure will also do the grading of this assignment.

Floating Point Standard

Single Precision Floating Point Format

Value is

If e = 255 and f ≠ 0, then v is NaN regardless of s

If e = 255 and f = 0, then v = (-1)s ∞

If 0 < e < 255, then v = (-1)s 2e- 127 (1.f)

If e = 0 and f ≠ 0, then v = (-1)s 2- 126 (x.f)

(denormalized numbers)(x is msb of value stored)

If e = 0 and f = 0, then v = (-1)s 0 (zero)

s e (8 bits) f (23 bits)

What to Check

• How to test the floating point multiplier for

both timing of inputs and outputs and

functional operation?

• Assume you have no knowledge of how

design is going to be implemented

The Test Vectors

Must test for normal operation and boundary conditions

A input by B input

NaN NaN

±Denorm ±Denorm

±Norm ±Norm

Denorm * OtherVal = Max Denorm

Denorm * OtherVal = Min Norm

Rounding using first guard bit

Rounding using 1st and 2nd guart bits

Applying Inputs to Design

Inputs are read

from a file and

applied to the

design

WHILE (NOT ENDFILE(test_data)) LOOP

--get next input test vector and expected result

readline(test_data,cur_line);

read(cur_line,aid); read(cur_line,a_test_val);

read(cur_line,bid); read(cur_line,b_test_val);

readline(test_data,cur_line);

read(cur_line,resid);read(cur_line,result_val);

std_result_val := To_StdLogicVector(result_val);

num_tests := num_tests + 1;

-- run through bus cycle to send data to unit

aid_sig <= "======", aid after 20 ns;

bid_sig <= "======", bid after 20 ns;

resid_sig <= "======", resid after 20 ns;

-- drive signals on bus

aval <= To_StdLogicVector(a_test_val) after 20 ns, HIGHZ after 80 ns;