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VTU 4TH SEM CSE MICROPROCESSORS NOTES 10CS45, Study notes of Microprocessors

Visvesvaraya Technological UniversityMicroprocessors

VTU 4TH SEM CSE MICROPROCESSORS NOTES 10CS45

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MICROPROCESSORS
(Common to CSE & ISE)
Subject Code: 10CS45 I.A. Marks : 25
Hours/Week : 04 Exam Hours: 03
Total Hours : 52 Exam Marks: 100
PART A
UNIT – 1 7 Hours
Introduction, Microprocessor Architecture – 1: A Historical Background, The Microprocessor-Based Personal
Computer Systems.
The Microprocessor and its Architecture: Internal Microprocessor Architecture, Real Mode Memory Addressing.
UNIT – 2 7 Hours
Microprocessor Architecture – 2, Addressing Modes: Introduction to Protected Mode Memory Addressing,
Memory Paging, Flat Mode Memory
Addressing Modes: Data Addressing Modes, Program Memory Addressing Modes, Stack Memory Addressing
Modes
UNIT – 3 6 Hours
Programming – 1: Data Movement Instructions: MOV Revisited, PUSH/POP, Load-Effective Address, String
Data Transfers, Miscellaneous Data Transfer Instructions, Segment Override Prefix, Assembler Details.
Arithmetic and Logic Instructions: Addition, Subtraction and Comparison, Multiplication and Division.
UNIT - 4 6 Hours
Programming – 2: Arithmetic and Logic Instructions (continued): BCD and ASCII Arithmetic, Basic Logic
Instructions, Shift and Rotate, String Comparisons.
Program Control Instructions: The Jump Group, Controlling the Flow of the Program, Procedures, Introduction to
Interrupts, Machine Control and Miscellaneous Instructions.
PART B
UNIT - 5 6 Hours
Programming – 3: Combining Assembly Language with C/C++: Using Assembly Language with C/C++ for 16-
Bit DOS Applications and 32-Bit Applications
Modular Programming, Using the Keyboard and Video Display, Data Conversions, Example Programs
UNIT - 6 7 Hours
Hardware Specifications, Memory Interface – 1: Pin-Outs and the Pin Functions, Clock Generator, Bus
Buffering and Latching, Bus Timings, Ready and Wait State, Minimum versus Maximum Mode.
Memory Interfacing: Memory Devices
UNIT – 7 6 Hours
Memory Interface – 2, I/O Interface – 1: Memory Interfacing (continued): Address Decoding, 8088 Memory
Interface, 8086 Memory Interface.
Basic I/O Interface: Introduction to I/O Interface, I/O Port Address Decoding.
UNIT 8 7 Hours
I/O Interface – 2, Interrupts, and DMA: I/O Interface (continued): The Programmable Peripheral Interface
82C55, Programmable Interval Timer 8254.
Interrupts: Basic Interrupt Processing, Hardware Interrupts: INTR and INTA/; Direct Memory Access: Basic DMA
Operation and Definition.
Text Book:
1. Barry B Brey: The Intel Microprocessors, 8th Edition, Pearson Education, 2009.
(Listed topics only from the Chapters 1 to 13)
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Download VTU 4TH SEM CSE MICROPROCESSORS NOTES 10CS45 and more Study notes Microprocessors in PDF only on Docsity!

( Common to CSE & ISE)

Subject Code: 10CS45 I.A. Marks : 25

Hours/Week : 04 Exam Hours: 03

Total Hours : 52 Exam Marks: 100

PART A

UNIT – 1 7 Hours

Introduction, Microprocessor Architecture – 1: A Historical Background, The Microprocessor-Based Personal

Computer Systems.

The Microprocessor and its Architecture: Internal Microprocessor Architecture, Real Mode Memory Addressing.

UNIT – 2 7 Hours

Microprocessor Architecture – 2, Addressing Modes: Introduction to Protected Mode Memory Addressing,

Memory Paging, Flat Mode Memory

Addressing Modes: Data Addressing Modes, Program Memory Addressing Modes, Stack Memory Addressing

Modes

UNIT – 3 6 Hours

Programming – 1: Data Movement Instructions: MOV Revisited, PUSH/POP, Load-Effective Address, String

Data Transfers, Miscellaneous Data Transfer Instructions, Segment Override Prefix, Assembler Details.

Arithmetic and Logic Instructions: Addition, Subtraction and Comparison, Multiplication and Division.

UNIT - 4 6 Hours

Programming – 2: Arithmetic and Logic Instructions (continued): BCD and ASCII Arithmetic, Basic Logic

Instructions, Shift and Rotate, String Comparisons.

Program Control Instructions: The Jump Group, Controlling the Flow of the Program, Procedures, Introduction to

Interrupts, Machine Control and Miscellaneous Instructions.

PART B

UNIT - 5 6 Hours

Programming – 3: Combining Assembly Language with C/C++: Using Assembly Language with C/C++ for 16-

Bit DOS Applications and 32-Bit Applications

Modular Programming, Using the Keyboard and Video Display, Data Conversions, Example Programs

UNIT - 6 7 Hours

Hardware Specifications, Memory Interface – 1: Pin-Outs and the Pin Functions, Clock Generator, Bus

Buffering and Latching, Bus Timings, Ready and Wait State, Minimum versus Maximum Mode.

Memory Interfacing: Memory Devices

UNIT – 7 6 Hours

Memory Interface – 2, I/O Interface – 1: Memory Interfacing (continued): Address Decoding, 8088 Memory

Interface, 8086 Memory Interface.

Basic I/O Interface: Introduction to I/O Interface, I/O Port Address Decoding.

UNIT 8 7 Hours

I/O Interface – 2, Interrupts, and DMA: I/O Interface (continued): The Programmable Peripheral Interface

82C55, Programmable Interval Timer 8254.

Interrupts: Basic Interrupt Processing, Hardware Interrupts: INTR and INTA/; Direct Memory Access: Basic DMA

Operation and Definition.

Text Book:

1. Barry B Brey: The Intel Microprocessors, 8th^ Edition, Pearson Education, 2009.

(Listed topics only from the Chapters 1 to 13)

TABLE OF CONTENTS

  • UNIT 1: INTRODUCTION TO MICOPROCESSOR & COMPUTER 1-
  • UNIT 2: THE MICROPROCESSOR AND ITS ARCHITECTURE(CONT.) 12-
  • UNIT 3: DATA MOVEMENT INSTRUCTIONS 32-
  • UNIT 4: ARITHMETIC AND LOGIC INSTRUCTIONS(CONT.) 59-
  • UNIT 6: 8086/8088 HARDWARE SPECIFICATIONS 68-
  • UNIT 7: MEMORY INTERFACE(CONT.) 81-
  • UNIT 8: BASIC I/O INTERFACE(CONT.) 85-

The Memory & I/O System

  • Normally, the memory contains 3 main parts:
    1. TPA(Transient Program Area)
    2. System Area &
    3. XMS(Extended Memory System)
  • If the computer is based upon 8086, the TPA and system-area exist, but there is no extended memory-area(Fig:1-7).
  • The PC contains → 640KB of TPA & → 384KB of system memory
  • The first 1Mbyte of memory is called real(conventional) memory because each microprocessor is designed to function in this area by using its real-mode of operation.
  • If the computer is based upon 80286, then 1)TPA 2)System area 3)Extended memory exist. These machines are called AT class-machines. (Sometimes, these machines are also referred to as ISA machines )
  • In the 80286, extended-memory contains up to 15MB (in addition to the first 1Mbyte of real memory).
  • The ISA machine contains an 8-bit peripheral-bus. The bus is used to interface 8-bit devices to the 8086-based computer.
  • In ATX class-systems, following 3 newer buses exist:
    1. USB(Universal Serial Bus) is used to connect peripheral-devices( such as keyboards and mouse) to the microprocessor through a serial data-path and a twisted-pair of wires. (Main idea: To reduce system cost by reducing the number of wires).
    2. AGP(Advanced Graphics Port) is used to transfer data between the video-card and the microprocessor at higher speeds(533 MB/s)
    3. SATA(Serial ATA) is used to transfer data from the PC to the hard-disk drive at rate of 150MB/s.

Figure 1-7: The memory map of a personal computer

TPA (Transient Program Area)

  • This holds i)DOS, ii)Application-programs and iii)Drivers that control the computer.
  • Length of TPA = 640KB (Fig: 1-8).
  • The memory-map of TPA contain following parts:
    1. The Interrupt-vectors access various features of the DOS, BIOS and applications.
    2. The system BIOS is a collection of programs stored in either a ROM or flash memory. This operates many of the I/O devices connected to the computer.
    3. The DOS communications areas contain transient-data used by programs to access → I/O devices and → internal features of the computer.
    4. The IO.SYS contains programs that allow DOS to use the keyboard, video-display, printer and other I/O devices.
    5. Device-drivers are programs that control installable I/O devices such as mouse, keyboard, CD-ROM memory, DVD.
    6. The COMMAND.COM program (command processor) controls the operation of the computer from the keyboard when operated in the DOS mode.

The System Area

  • This contains memory used for video-cards, disk-drives and the BIOS ROM.
  • This contains → programs on either a ROM or flash memory & → areas of RAM for data-storage.
  • The area at locations C8000H-DFFFFH is open(or free). This area is used for the expanded memory system(EMS) in the computer.
  • The EMS allows a 64Kbyte page-frame of memory to be used by application-programs.
  • Finally, the system BIOS ROM controls the operation of the basic I/O devices connected to the computer.

Figure 1-8:The memory map of the TPA in a PC Figure 1-9:The system area of a typical PC

Buses

  • A bus is a common group of wires that interconnect components in a computer (Fig 1-12)
  • The buses transfer address-, data- and control-information between → microprocessor & its memory → microprocessor & I/O
  • Three types of buses are used for transfer of information: i)address, ii)data and iii)control. Address Bus
  • The address-bus is used to request → a memory-location(from the memory) or → an I/O location(from the I/O devices)
  • If I/O is addressed, the address-bus contains a 16-bit I/O address. The 16-bit I/O address (or port number) selects one of 64K different I/O devices.
  • If memory is addressed, the address-bus contains a memory-address (which varies in width with the different versions of the microprocessor).
  • 8086 address 1M byte of memory using a 20-bit address that selects locations 00000H-FFFFFH. 80286 address 16MB of memory using a 24-bit address that selects locations 000000H-FFFFFFH. Data Bus
  • The data bus is used to transfer information between → microprocessor and memory → microprocessor and I/O address-space.
  • A 16-bit data bus transfers 16 bits of data at a time.
  • The advantage of a wider data bus is speed in applications that use wide data.(For example, if a 32 bit number is stored in memory, it takes the 8086 microprocessor two transfer operations to complete because its data bus is only 16 bits wide). Control Bus
  • The control-bus → controls the memory & I/O and → requests reading or writing of data
  • There are 4 control-bus connections:
    1. MRDC (memory read control),
    2. MWTC (memory write control),
    3. IO RC

(I/O read control) and

  1. (^) IOWC (I/O write control) {The overbar indicates that the control signal is active-low i.e. it is active when a logic zero appears on the control line. For example, if (^) IOWC =0, the microprocessor is writing data from the data bus to an I/O device whose address appears on the address bus}
  • Steps to read (or fetch) data from memory:
    1. Firstly, microprocessor sends an address (of a memory-location) through the address bus to the memory
    2. Next, it sends the MRDC signal to cause the memory read data
    3. Finally, the data read from the memory are passed to the microprocessor through the data bus

Figure 1-12: The block diagram of a computer system showing the address, data and control bus structure

The Intel family of microprocessor bus and memory sizes Microprocessor Data bus width Address bus width Memory size 8088 8 20 1M 8086 16 20 1M 80286 16 24 16M 80386DX 32 24 4G Pentium 64 32 4G Pentium Pro Core

64 40 1T

Itanium 128 40 1T

Figure 1-13: The physical memory systems of the 8086 and 80286

Binary Coded Hexadecimal (BCH)

  • This is used to represent hexadecimal data in binary-code.
  • A binary-coded hexadecimal number is a hexadecimal number written so that each digit is represented by a 4- bit number.
  • The assembler is a program that is used to program a computer in its native binary machine language.
  • Hexadecimal memory addresses (memory locations) are used to number each byte of the memory system. A hexadecimal number is a number represented in base 16, with each digit representing a value from 0 to 9 and A to F

Hexadecimal digit =>BCH code 0=> 0000 1=> 0001 2=> 0010 3=> 0011 4=> 0100 5=> 0101 6=> 0110 7=> 0111 8=>1000 9=> A=>1010 B=>1011 C =>1100 D=>1101 E=> 1110 F=> 1111 Example 1: 2AC =>0010 1010 1100 1000 0011 1101. 1110 =>83D.E

Multipurpose Registers

RAX(Accumulator)

  • AX is used for instructions such as multiplication & division instructions (Figure 2-1).
  • In 80386, the EAX may also hold the offset-address of a location in the memory. RBX(Base Index)
  • BX holds the offset address of a location in the memory.
  • In 80386, EBX also can address memory-data. RCX(Count)
  • CX holds the count for various instructions.
  • The shift & rotate instructions use CL as the count the repeated string & loop instructions use CX as the count. RDX(Data)
  • DX holds → a part of the result from a multiplication or → a part of the dividend before a division RBP(Base Pointer)
  • BP points to a memory-location for memory data-transfers. RDI(destination Index)
  • DI addresses string destination-data for the string instructions. RSI(Source Index)
  • SI addresses source string-data for the string instructions. R8 through R
  • These are only found in the Pentium if 64-bit extensions are enabled.

Special Purpose Registers

RIP(Instruction Pointer)

  • It is used by the microprocessor to find the next sequential instruction in a program located within the code- segment.
  • It can be modified with a jump or a call instruction. RSP(Stack Pointer)
  • It addresses an area-of-memory called the stack.
  • The stack-memory stores data through this pointer.

Segment Registers

  • Segment-registers generate memory-addresses when combined with other registers. CS(Code)
  • The code-segment is a section-of-memory that holds the code(programs & procedures) used by the microprocessor.
  • CS register contains the starting-address of the code-segment.
  • In real-mode operation, it defines the start of a 64Kbyte code-segment. In protected-mode, it selects a descriptor that describes the starting-address and length of a code- segment memory.
  • The code-segment is limited to → 64 KB in the 8086 and → 4 GB in the 80386 DS(Data)
  • The data-segment is a section-of-memory that contains most data used by a program.
  • Data are accessed in the data-segment by an offset-address (or the contents of other registers that hold the offset-address). ES(Extra)
  • The extra-segment is an additional data-segment that is used by some of the string instructions to hold destination-data. SS(Stack)
  • The stack-segment is a section-of-memory used for the stack.
  • The stack entry-point is determined by the stack-segment(SS) and stack-pointer(SP) registers. FS and GS
  • The FS and GS segments allow 2 additional memory segments for access by programs in 80386 microprocessor.

RFLAGS

  • This register indicates the condition of the microprocessor and controls its operation (Figure 2-2).

Figure 2-2:The EFLAG register of microprocessor family C(Carry)

  • Carry holds the carry after addition or the borrow after subtraction.
  • The carry flag also indicates error conditions (as dictated by some programs and procedures). P(Parity)
  • Parity is logic 0 for odd-parity and logic 1 for even-parity.
  • Parity is the count of 1s in a binary-number expressed as even or odd. For example, if a number contains three binary 1 bits, it has odd-parity. A(Auxiliary Carry)
  • The auxiliary-carry holds the carry after addition (or borrow after subtraction) between bit-positions 3 and 4 of the result.
  • This flag bit is tested by the DAA or DAS instructions to adjust the value of AL after a BCD addition or subtraction. Z(Zero)
  • Zero flag shows that the result of an arithmetic or logic operation is zero. If Z=1, the result is zero; if Z=0, the result is not zero. S(Sign)
  • Sign flag holds the sign of the result after an arithmetic or logic instruction executes. If S=1, the sign bit is set(or negative); if S=0,the sign bit is cleared(or positive). T(Trap)
  • If T=1, the microprocessor interrupts the flow of the program on conditions as indicated by the debug registers and control registers. If the T=0, the trapping feature is disabled. I(Interrupt)
  • This flag controls the operation of the INTR(interrupt request) input pin. If I=1, the INTR pin is enabled; if I=0, the INTR pin is disabled.
  • The I flag is set with STI(set I flag) and cleared with the CLI(clear I flag) instructions. D(Direction)
  • The direction flag selects either the increment or decrement mode for the DI or SI registers during string instructions.
  • If D=1, registers are automatically decremented; if D=0, registers are automatically incremented.
  • The D flag is set with STD(set direction) and cleared with the CLI(clear direction) instructions. O(Overflow)
  • Overflows occur when signed-numbers are added or subtracted.
  • An overflow indicates that the result has exceeded the capacity of the machine. IOPL(I/O Privileged Level)
  • IOPL is used to select the privilege-level for I/O devices.
  • If current privilege-level is higher or more trusted than the IOPL, I/O executes without difficulty. If current privilege-level is lower than the IOPL, an interrupt occurs, causing execution to suspend. NT(Nested Task)
  • This flag indicates that the current task is nested within another task. RF(Resume)
  • This flag is used with debugging to control the resumption of execution after the next instruction. VM(Virtual Mode)
  • This flag selects virtual mode operation. AC(Alignment Check)
  • This flag activates if a word is addressed on a non-word boundary. VIF(Virtual Interrupt)
  • This is a copy of the interrupt flag bit available to the Pentium4 microprocessor. VIP(Virtual Interrupt Pending)
  • This is used in multitasking environments to provide the operating-system with virtual interrupt flags and interrupt pending information. ID(Identification)
  • This flag indicates that the Pentium4 microprocessor supports the CPUID instruction.

Segment & Offset Addressing Scheme Allows Relocation

  • This scheme allows both programs and data to be relocated in the memory (Figure 2-4).
  • This also allows programs written to function in the real-mode to operate in a protected-mode system.
  • Relocatable-program can be placed into any area of memory and executed without change.
  • Relocatable-data can be placed in any area of memory and used without any change to the program.

Figure2-4: A memory system showing the placement of four memory segments

Table 2-2: Example of real mode segment addresses

UNIT 2: THE MICROPROCESSOR AND ITS

ARCHITECTURE(CONT.)

Introduction to Protected Mode Memory Addressing

  • Protected-mode memory addressing(80286) allows access to data & programs located → above first 1MB of memory & → within first 1MB of memory.
  • In place of segment-address, segment-register contains a selector that selects a descriptor from a descriptor- table. (The extended memory system is accessed via a segment-address plus an offset-address, just as in the real mode. The difference is that the segment-address is not held in the segment-register. In the protected-mode, the segment starting-address is stored in a descriptor that is selected by the segment-register).
  • Descriptor describes → memory-segment's location → length & → access rights
  • Another difference in the 80386 is that the offset-address can be a 32-bit number instead of a 16-bit number.

Figure 2-9: Using DS register to select a descriptor from the global descriptor table

Access Rights Byte

  • This controls access to the protected-mode segment. This byte describes how the segment functions in the system.
  • If the segment is a data-segment, the direction of growth is specified. If the segment grows beyond its limit, the operating-system program is interrupt to indicate a general protection-fault.
  • The RPL(request privilege level) requests the access privilege-level of a memory-segment. If the RPL is higher than the privilege-level set by the access rights byte, access is granted.
  • The segment-register contains 3 fields of information: → Selector(First 13 bits) address one of 8192 descriptors from a descriptor-table. → TI bit selects either global descriptor-table(TI=0) or local descriptor-table(TI=1). → RPL(Last 2 bits) select the requested priority level for the memory segment access.

Figure 2-7:The access rights byte for the 80286 descriptor

Figure 2-8: The contents of a segment register during protected mode operation of the 80286 microprocessor

Memory Paging

  • Memory-paging mechanism allows any physical memory-location to be assigned to any linear-address.
  • The linear-address is defined as the address generated by a program The physical-address is the actual memory-location accessed by a program.

Paging Registers

  • Memory-paging is accomplished through control-registers CR0 and CR3.
  • The paging-unit is controlled by the contents of the control-registers.
  • The leftmost bit(PG) position of CR0 selects paging when placed at a logic 1 level. If PG bit is cleared(0), linear-address generated by program becomes physical-address used to access memory. If PG bit is set(1), linear-address is converted to a physical-address through paging-mechanism.
  • The page directory base-address locates the directory for the page translation-unit.
  • If PCD is set(1),the PCD pin becomes a logic one during bus cycles that are not paged.
  • The page-directory contains upto 1024 entries that locate physical-address of a 4KB memory-page.
  • The linear address is broken into 3 sections:
    1. Page directory selects a page table that is indexed by the next 10 bits of the linear-address
    2. Page table entry
    3. Offset part selects a byte in the 4KB memory-page
  • In 80486, the cache (translation look aside buffer-TLB) holds the 32 most recent page translation addresses.

Figure 2-11:The control register structure of the microprocessor

Figure 2-12: The format for the linear address

Flat Mode Memory

  • In a Pentium-based computer, the memory-system that uses the 64-bit extensions uses a flat mode memory.
  • A flat mode memory system is one in which there is no segmentation.
  • The flat model does not use a segment-register to address a location in the memory.
  • The CS segment-register is used to select a descriptor from the descriptor-table that defines the access rights of only a code-segment.
  • The segment-register still selects the privilege-level of the software.
  • The flat model does not select the memory-address of a segment using the base and limit in the descriptor.
  • The flat mode memory contains 1TB of memory using a 40-bit address.

Figure 2-15: The 64-bit flat mode memory model