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VTU 4TH SEM CSE MICROPROCESSORS NOTES 10CS45
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PART A
PART B
The Memory & I/O System
Figure 1-7: The memory map of a personal computer
TPA (Transient Program Area)
The System Area
Figure 1-8:The memory map of the TPA in a PC Figure 1-9:The system area of a typical PC
(I/O read control) and
Figure 1-12: The block diagram of a computer system showing the address, data and control bus structure
The Intel family of microprocessor bus and memory sizes Microprocessor Data bus width Address bus width Memory size 8088 8 20 1M 8086 16 20 1M 80286 16 24 16M 80386DX 32 24 4G Pentium 64 32 4G Pentium Pro Core
Itanium 128 40 1T
Figure 1-13: The physical memory systems of the 8086 and 80286
Binary Coded Hexadecimal (BCH)
Hexadecimal digit =>BCH code 0=> 0000 1=> 0001 2=> 0010 3=> 0011 4=> 0100 5=> 0101 6=> 0110 7=> 0111 8=>1000 9=> A=>1010 B=>1011 C =>1100 D=>1101 E=> 1110 F=> 1111 Example 1: 2AC =>0010 1010 1100 1000 0011 1101. 1110 =>83D.E
RAX(Accumulator)
RIP(Instruction Pointer)
Figure 2-2:The EFLAG register of microprocessor family C(Carry)
Segment & Offset Addressing Scheme Allows Relocation
Figure2-4: A memory system showing the placement of four memory segments
Table 2-2: Example of real mode segment addresses
UNIT 2: THE MICROPROCESSOR AND ITS
ARCHITECTURE(CONT.)
Introduction to Protected Mode Memory Addressing
Figure 2-9: Using DS register to select a descriptor from the global descriptor table
Access Rights Byte
Figure 2-7:The access rights byte for the 80286 descriptor
Figure 2-8: The contents of a segment register during protected mode operation of the 80286 microprocessor
Memory Paging
Paging Registers
Figure 2-11:The control register structure of the microprocessor
Figure 2-12: The format for the linear address
Flat Mode Memory
Figure 2-15: The 64-bit flat mode memory model