Cache Coherence
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VLSI Design and Computer architecture, Lecture notes of Advanced Computer Architecture
Course study for Computer architecture subdesign
Typology: Lecture notes
2016/2017
1 / 13
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Cache Coherence
Symmetrical Architecture
Multiprocessor (SMP)
(^) All Processors have
access to all the resources of the system
(^) Bus Based: All memory
locations equal access time. Hence SMP.
(^) For reasons of
performance each processor will have its own cache
Cache Coherence Protocol
Characteristics
Mechanisms to supervise modifications to
block.
Update mechanisms for modified blocks.
State diagrams for the blocks
Supervise Modification to Blocks
(^) Protocol based on monitoring all traffic (snooping)
- (^) Each processor observes all transactions on the processor-memory interconnect to see if the transaction refers to a block which it holds in its cache
- (^) State of each block may then be modified appropriately in accordance with the bus transactions
- (^) Disadvantage (^) Increases Bus Traffic. (^) Offers a barrier to scalability
Update mechanisms for Modified
blocks
Write Invalidate:
- (^) The processor wishing to write the data must first invalidate of all the copies of the data in the caches of the other processors, it may then proceed to update the data in its cache.
- (^) First puts an invalidate transaction on the bus, specifying the address of the block affected.
- (^) All the other processors check for the presence of the block in their own caches, and, if it is present, invalidate it.
Update mechanisms for Modified
blocks
Write Update:
- (^) Rather than invalidating other copies, in this scheme the updated information is broadcasted on the bus.
- (^) The other processors update their copies with the new value.
- (^) This Process is also called as Write Broadcast
State diagrams for the blocks
(^) Falls into family of protocols called MESI (Modified,
Exclusive, Shared, Invalid).
- (^) Modified: The block is valid, and has been changed by its processor, and is the only cached copy of the data in the system
- (^) Exclusive. The block is valid, and is the only cached copy in the system, and has not been modified by its processor
- (^) Shared. The block is valid and there is at least one other copy of the block in another processor's cache.
- (^) Invalid. The block is invalid; any access to this block (in this cache) will lead to a cache miss
State diagrams for the blocks
P1 - Processor 1
P2 - Processor 2
Other Protocols
- (^) MSI protocol
- (^) MESI protocol
- (^) MOSI protocol
- (^) MOESI protocol
- (^) Write-once protocol
- (^) Synapse protocol
- (^) Berkeley protocol
- (^) Illinois protocol
- (^) Firefly protocol
- (^) Dragon protocol