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Advanced Digital Design: Lecture Notes on Sequential Circuits and State Machines, Study notes of Electrical and Electronics Engineering

Lecture notes on advanced digital design, focusing on creating combinational circuits using development systems. It covers topics such as functional simulation, state machine designs, determining fmax, clock skew, and various design techniques. Numerous examples are included to help students understand the concepts.

Typology: Study notes

Pre 2010

Uploaded on 08/18/2009

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ECPE174
ADVANCED DIGITAL DESIGN
LECTURE NOTES
===================================================================
===================================================================
USING DEVELOPMENT SYSTEMS TO CREATE COMBINATIONAL CIRCUITS
- Circuits can be designed much the same as when using discrete logic ...
1. DESIGN
- all you need is Schematic Capture software
- or use PALASM or VHDL or Verilog
- just make sure the logic blocks you use are available in the software's library
- you can create your own hardware macros to create your own ALUs, for example.
2. FUNCTIONAL SIMULATION
- checks for proper function, but does not account for circuit delays (not known yet - not
until actually in PLD)
3. ROUTING
- a router determines how to configure & interconnect FPGA modules to produce your
circuit. It may require some help from you. It may request circuit simplification. It may not be
able to get your whole design on 1 FPGA, requiring you to split the designbetween two or more
FPGAs.
4. BACK ANNOTATION
- the development system determines the circuit delays and back annotates those delays
into the simulation.
5. SIMULATION - The normal steps of logic design should be:
a. block diagram
b. schematic capture, HDL
c. computer simulation
d. redesign/re simulation until it works
e. prototype and testing
5. PROGRAMMING
- some PLDs can be programmed only once. XILINX uses RAM, however. ALTERA
uses true EPLDs; however, its largest PLDs also use RAM to store program data.
6. TESTING - if it doesn't work, start over.
===================================================================
===================================================================
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ECPE

ADVANCED DIGITAL DESIGN

LECTURE NOTES

USING DEVELOPMENT SYSTEMS TO CREATE COMBINATIONAL CIRCUITS

  • Circuits can be designed much the same as when using discrete logic ...
  1. DESIGN
  • all you need is Schematic Capture software
  • or use PALASM or VHDL or Verilog
  • just make sure the logic blocks you use are available in the software's library
  • you can create your own hardware macros to create your own ALUs, for example.
  1. FUNCTIONAL SIMULATION
  • checks for proper function, but does not account for circuit delays (not known yet - not until actually in PLD)
  1. ROUTING
  • a router determines how to configure & interconnect FPGA modules to produce your circuit. It may require some help from you. It may request circuit simplification. It may not be able to get your whole design on 1 FPGA, requiring you to split the designbetween two or more FPGAs.
  1. BACK ANNOTATION
  • the development system determines the circuit delays and back annotates those delays into the simulation.
  1. SIMULATION - The normal steps of logic design should be: a. block diagram b. schematic capture, HDL c. computer simulation d. redesign/re simulation until it works e. prototype and testing
  2. PROGRAMMING
  • some PLDs can be programmed only once. XILINX uses RAM, however. ALTERA uses true EPLDs; however, its largest PLDs also use RAM to store program data.
  1. TESTING - if it doesn't work, start over. =================================================================== ===================================================================

ANALYSIS - State Machine designs LOTS of EXAMPLES (1) Is it a MEALY or a MOORE machine? (2) Determine the State Diagram and State Table

  • It may help to determine the Next State logic functions.
  • I.e. the functions for Qi(next) and for the outputs
    • This is called SYMBOLIC ANALYSIS =================================================================== DETERMINING Fmax EXAMPLES METASTABILITY - If the possibility of not meeting SET-UP or HOLD Times exists, the behavior becomes non-deterministic. That is, the circuit exhibits meta-stability. Later, we will learn how to prevent meta-stability. =================================================================== TIMING DIAGRAMS EXAMPLES =================================================================== CLOCK SKEW Clock skew occurs when the clock edge arrives at different FFs at different times. Therefore the state transition is Not precise. Glitches can occur on the output if more than one FF is supposed to change state. Be aware of this as you design. If only one FF can change state at each clock transition, no problem. Otherwise, ask yourself, "Can the system withstand glitches at the output?" It can if the output is going to a Lamp, for example. If it cannot, then deglitch the output, as shown later, in the discussion of design implementation. =================================================================== EXAMPLE: Converting between D and JK flip-flops

Examine SELF-CORRECTING machines, which get back into correct operation whenever they inadvertently enter an unused state.

  1. Design a state machine that detects three 1s in a row in an input, X.
  2. Design a state machine that detects two 1s (not necessarily in a row).
  3. Design a state machine that detects two 1s, but they cannot be in a row.
  4. Design a state machine the detects two 1s and sets its output high for two clock cycles. The input is ignored while the output is high.
  5. Design a state machine that samples the input in 3-bit windows. If a majority of the bits are high, the output is set high and the circuit locks up, holding the output high. =================================================================== One-Hot Design It's simple - just have one flip-flop per state. It's fast - no Karnaugh maps Can often assign an output to be active in just one state and therefore the output is simply one of the FF-Q outputs, eliminating glitches in outputs. But can get more complex IFL
    • GREAT for PALs because can see state and output equations directly from state diagram! THEREFORE, design time is short - no K-maps. BUT good ONE-HOT design is generally a matter of judgment and trial and error. EXAMPLES: =================================================================== =================================================================== CHAPTER 10 - SEQUENTIAL DESIGN: IMPLEMENTATION =================================================================== =================================================================== DEBOUNCING switch inputs using an SR (set/reset) latch
  • just use two NAND gates and a SPST switch =================================================================== SYNCHRONIZING the Inputs

RULE: If branching transitions out of a state depend on a single asynchronous input, the codes for the branch states should be logic-adjacent, i.e. they should differ in only 1 bit.

  • have only one flip-flop change state at a time!
  • otherwise, one flip-flop may have its tsu met and another may not.
  • especially when the number of gate delays differs for each flip-flop input RULE: Synchronize all input changes on the edge of the clock that does not change the state. (Best when clock has 50% duty cycle.) To do this, use a FF on each input. Run each signal to the D FF input and run an Inverted clock to the clock input. Of course, this assumes a relatively slow-changing input, that has pulses that are at least as wide as the clock period. If this is not the case, Speed Up The Clock! ================================================================== DEGLITCHING the Outputs
  • Glitches are unwanted short-duration changes in the output of a state machine that occur as the machine changes state. EX: When one want an o/p HIGH in state 11 and the machine goes from state 01 to 10, but bit 1 changes faster than bit 0 (smaller tp).
  • The problem can also be caused by variable gate delays. SOLN: Same as with asynchronous inputs (that have not been made synchronous with a FF)
  • don't let more than 1 flip-flip change states at a time In any case where you cannot avoid having more than 1 state bit change at a time, you have 3 choices: (1) Delay the output one clock cycle by latching it into FFs (or register) and clocking the FFs with the clock (2) Delay the output 1/2 clock cycle by latching it into FFs And clocking with an inverted clock (3) Delay as little as possible by using the regular clock, But delaying it minimally with pairs of inverters. Note that PROM-based outputs will have glitches as the PROM's address inputs change. We often use a deglitching register on the outputs of a PROM (as will see later, when doing many- State Machine design. =================================================================== STATE CODE ASSIGNMENT We choose specific state assignments to:

EXAMPLES

  1. Implement a non-resetting sequence detector ...
  • e.g. using a 4:16 decoder
  • e.g. using gates and D FFs
  1. Design a resetting Moore Machine that detects the number 9 In binary...
  2. Design a Mealy Machine to control an elevator (Problem 10.5)
  3. Design a 4-bit ripple up-counter using D FFs. Timing Diagrams =================================================================== =================================================================== IMPLEMENTING STATE MACHINES IN SOFTWARE At the end of the semester, we will look at the design of CPUs and even design on into a FPGA in the lab. BUT here, we are NOT talking about designing a computer, BUT rather using one to as a state machine (after all, that's what it is) to simulate and test a sequential design. Note that a computer does have memory and the code acts as the decision logic. Writing a program to test a sequential design is not as often done as it used to be because of today's available simulation software - it's built into PALASM, for example. HOWEVER, it is still true that is sometimes faster, easier, and/or cheaper to simply implement a sequential machine (control system) in a PC, using either standard (e.g. the parallel port) or custom I/O boards to interface to the i/ps and o/ps. Compare uP-based systems. For testing purposes, the keyboard can be used to simulate inputs, and the monitor can be used to display simulated outputs - whether or not the final system will reside in the computer. TWO REASONS why we would NOT use a computer to implement a state machine:
    1. The design is too simple to tie up a whole computer.
    2. The needed speed is too great for a computer to do the job.

BUT don't forget: A -PC- may be an ideal solution to many problems:

  1. The are generally inexpensive.
  2. It is easy to just add an I/O card & then write the software in an HLL.
  3. The software is easily modified for changing requirements. =================================================================== =================================================================== VERY LARGE STATE MACHINE DESIGN Such systems are often complex controllers that carry a system through many states
  • or more often, states of different duration In general, we have no branching -- but we can, for example, in the case of a computer control unit design (we just use a parallel loadable counter). (Note: - When states are long-lasting and have much branching, better to use a PC and do the job in software using delay loops. You must know clock frequency and the number of states per instruction.) We can't use the techniques we've been using so far! (too many FFs, K-maps, huge state tables, etc.) We use counters (such as the 74LS163), PROMS, and latches
  • to deglitch the outputs. It's simple -- use a large counter, and have the counter output be the state number
  • easiest to use a ROM to decode the state (serving as the OFL) EXAMPLE: Specifications: Repeat the following every 31,100ns: PROC1: high for 100ns at 500ns, 1000ns, 1500ns,....until 10,000ns PROC2: high for 200ns at 500ns, 21,000ns, and 28,000ns PROC3: high for 500ns at 800ns and 15,000ns END: high for 100ns at 31,000ns RST: an active-low reset (sets "timer" to zero) All outputs must be glitch-free. DRAW a partial Timing Diagram. Solution: We can see that we need a resolution of 100ns; therefore will use a clock of 10 MHz. Therefore we will require 311 states (0 through 310) - will need 9 bits (29 = 512). We will cascade three 74LS163s (4-bit synchronous counters with synchronous clear).
  • will activate the CLEAR (a 5th o/p) input on count of 310 (next clock will clear). We will use a 2Kx8 ROM to decode the outputs.
  • 11 input bits (ground the top 2 bits); 8 output bits (n/c on 3 of them).