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Your Name: _______________________________________
Quiz2 Page 1 of 10 CS 150 - Sp. 94
UN IVERSIT Y OF CA LIFORNIA AT BERKELEY
BER KELEY • D AV IS • IR VIN E • LO S A N GELES • RIVERS ID E • S AN D IEGO • S AN FRANCIS CO SA NTA BA RBA RA • S AN TA CRU Z De p a r tm en t of Ele ct r i ca l En gin e e ri n g a n d Com p u t e r Sci en c es
CS 1 5 0 - Spr i n g 1 99 4 Pr o f. A. R. Ne wt o n
Quiz 2
Room 145 Dwinelle, Tuesday 4/ (Open Katz, Calculators OK, 1hr 20min)
Include all final answers in locations indicated on these pages. Use reverse side of sheets for all working. If necessary, attach additional sheets by staple at the end. BE SURE TO WRITE YOUR NAME ON EVERY SHEET.
(1) Consider the logic schematic diagram shown below:
D C
Q Q
D C
Q Q
Y1 Z
Y
X
CLK
(a) Is this a Moore or Mealy machine? ________________ (2pts)
(b) What are the next-state and output equations for this machine? (9pts)
(i) Y1 = ____________________________________________________________________
(ii) Y2 = ____________________________________________________________________
(iii) Z = ____________________________________________________________________
CS 150 - Sp. 94 Page 2 of 10 Quiz
(c) Draw a state transition graph (STG) for the machine showing all possible states and all possible transitions (7pts)
(d) Does the machine contain any redundant states? If so, which state(s) are redundant and how can they be removed? Draw an irredundant STG for the machine. (7pts)
CS 150 - Sp. 94 Page 4 of 10 Quiz
(c) If the idle state is encoded as Y1 Y2 = 0 0, State A is encoded as Y1 Y2 = 0 1 and State B as Y1 Y = 1 1, derive the Karnaugh maps for the next-state and output functions. (4pts)
Y1' Y2' OA OB
(d) If the machine is to be implemented using JK flip-flops , obtain the Karnaugh maps for the JK flip- flop excitation inputs. Write the excitation input and external output equations for the design. (10pts)
J1 J2 K1 K
J1 = ______________________________________________________________
J2 = ______________________________________________________________
K1 = _____________________________________________________________
K2 = _____________________________________________________________
OA= _____________________________________________________________
OB = _____________________________________________________________
Your Name: _______________________________________
Quiz2 Page 5 of 10 CS 150 - Sp. 94
(e) Show a schematic diagram for the bus arbiter using positive edge-triggered JK flop flops. (3pts)
Extra space for Problem 2
Your Name: _______________________________________
Quiz2 Page 7 of 10 CS 150 - Sp. 94
(b) Use an implication table to find all possible pairs of equivalent or compatible states (3pts).
(c) Construct a merger diagram from the results of (b) and list the sets of mergeable states that will lead to the minimum number of states for the design. (3pts)
(d) Obtain a reduced flow table from the above, giving a unique state name to each group of states merged into a single state (hint: I ended up with 3 merged states, in Moore form). (3pts)
CS 150 - Sp. 94 Page 8 of 10 Quiz
(e) Examine the reduced flow table and add additional states if necessary to obtain a critical-race- free state assignment for the circuit. (hint: requires two state bits) (3pts)
(f) Construct a composite Karnaugh map for the next-state and external output logic functions from your state assignment. (3pts)
- CS 150 - Sp. 94 Page 10 of 10 Quiz
- Additional space for Problem
