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1
of
8
Problem 1
(16 points)
List the ROM contents in
hexadecimal
to implement the FSM shown below. The inputs A and B are synchro-
nized. The states are assigned numerical order, e.g., for state S4, Q
Q 2
Q 1
0
. (Follow normal state diagram 2
assumptions: holding in the same state is implicit, etc.).Fill in ROM contents in hexadecimal. (Binary answers will receive no credit.)
Address
Data
01 2 3 4 56 7
Address
Data
89 ABCDEF
Address
Data
1011121314151617
Address
Data
1819 1A1B1C1D1E1F
RESET
X/
S
S
S
S
S
S
S0 S
X/
X/ X/
X/
X/
AB
(^11) ⁄
AB
(^11) ⁄ A^
(^10) ⁄
AB
(^00) ⁄
A^
(^10) ⁄
X = don’t careformat:
AB
/out2out
AB
(^00) ⁄
A4A3A2A1 A
O4O3 O2O1 O
D2D1D
Q2Q1Q
Q2Q1Q
AB
Q2Q1Q
OUT2 OUT
RESET (synchronous)RESET CLOCK
ROM 32
×^5
2 of
Problem 2
(25 points)
Your coworker suggests using the circuit below in a Xilinx XC4005A-4 to create a global clock signalCLOCKOUT. [2 pts.]
a)
In 10 words or less, what is the intended function of this circuit? (Be as specific as possible.)
[15 pts.] b)
Complete the timing diagram for this circuit using the given data. (Interconnect delay is betweenany CLBs.) You should exaggerate the horizontal scale as needed to show important timing details.
Parameter
Value
CLOCKIN
10 MHZ
interconnect delay
2ns < T
ID
< 10ns
combinatorial delay
T ILO max
= 4.0ns
setup time
T ICK
= 4.5ns
hold time
0ns min
clock to output delay
T CKO max
= 3.0ns
clock skew
< 0.1ns
CLOCKOUT
BUFGS
D
Q
CLOCKIN
BUFGS
Q
D
D
0
Q
1
Q
0
CLB
CLB
CLB
Q
0 Q
1
CLOCKIN CLOCKOUT
3
of
8
[5 pts.]
c)
Explain in 25 words or less why or why not this circuit will always function as intended.
[3 pts.]
d)
If the circuit did function correctly, what would the minimum clock period be? (Leave in algebraicform, e.g.,
period
2 T
ILO
period
4 of
Problem 3
(10 points)
A bus of length 20m with propagation velocity of
has a driver at the transmitting end with reflec-
tion coefficient of 0 and a receiver at the opposite end with a reflection coefficient of +1. Initially, the bus is at 0V.At time
, a step of amplitude 2V starts propagating from transmitter output to receiver input.
Sketch
, the voltage at the midpoint of the line, for
. Assume the measurement at
has
no effect on the transmission line.
8
×
ms
(^1) –
t^
0ns
L^
S^
V
mid
V
mid
t^
1000ns
<
V
mid
V
mid
(volts) 8765 4321
t^
(ns)
1000
800
700
600
500
400
300
200
100
900
7
of
8
Problem 5
(25 points)
In this problem you will design the FSM controller for the serial transmitter shown below. The serial format is avariety of a
self-clocking
scheme. At the start of every bit, Serial Out changes state. A transmitted “0” is 4 clock
cycles long, and a transmitted “1” is 2 clock cycles long. The transmitter loads 4 bits
in parallel and
sends the data out MSB first. All parts have synchronous reset and load. Assume next 4 bits are ready whenLOAD is asserted.
when counter
[15 pts.] a)
Complete the timing diagram for the signals SHIFT and LOAD to get proper operation of the serialtransmitter, for data
. Please also label states on timing diagram. Assume delays
are small with respect to clock period.
B
3
B
B 2
B 1
0
T
D
Q
CLOCK
2 Bit Sync. Counter
R D 0 D 1
SHIFT^ LOAD
RESET COUNT
CLOCK
R
SHIFTRESET
SERIAL OUT
CLOCK
4 Bit Loadable Shift
Left Register
LOADSHIFT
B^ ^4
Q
3
Q 3
Data Path Block Diagram
Controller Block Diagram
FSM
RESET
Q 3
COUNT
SHIFTLOAD
CLOCK
Toggle FF
CE
L TC
L CE
(load has precedence over shift)
+5V
Q
1 Q
0
not used
TC
Q
Q 1
0
B
3
B
B 2
1
B
0
StateClock Reset
SerialOut
SHIFTLOAD
B3‘‘0”
B2‘‘1”
B1‘‘1”
B0‘‘0”
S^0
S^0
S^0
next B
COUNT
8 of
[10 pts.] b)
Complete the state diagram for a Mealey FSM which will generate the proper control signals for thetiming diagram above and proper control of the transmitter. All transitions should be labelled explic-itly in the format Q
3
COUNT3/SHIFT LOAD. Use “X” for “don’t care.
S
0
S
S^13
S
2
RESET/RESET
