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Understanding the Arithmetic Logic Unit (ALU) in Computer Processors - Prof. Edward Boswor, Study notes of Computer Architecture and Organization

The basics of the arithmetic logic unit (alu) in a computer processor, focusing on its construction from simple circuits, limited operations including boolean operators, transfer operations, and addition. It also discusses the logical functions of the alu and the implementation of logical operations using boolean gates.

Typology: Study notes

Pre 2010

Uploaded on 08/04/2009

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The Arithmetic Logic Unit
We now consider the ALU (Arithmetic Logic Unit) of the CPU (Central Processor Unit) of
the computer and show how it is built from the circuits that we have previously considered.
We shall begin with a very simple ALU, with a limited set of operations that include three
Boolean operators (AND, OR, and NOT), simple transfer operations, and addition.
The reader will note that three of the above operations (AND, OR, and addition) are dyadic;
that is, they require two arguments and produce one output. To accommodate this fact, all
modern arithmetic logic units are constructed with two input busses and one output bus.
Operations, such as W = X + Y + Z (adding three arguments) are always broken down into a
sequence of dyadic operations in order to avoid great complexity in the CPU.
The standard symbol for an ALU is shown in the figure below. The naming of the three
busses is this author’s own notation, though similar to that used by other authors. Flow is
from top to bottom; B1 and B2 are the input busses, and B3 is the output bus.
As an aside at this point, we note that the three–bus ALU dictates a CPU with at least three
internal busses, which are separate from the system bus that connects the CPU to memory
and I/O devices. The figure below shows a rough view of the CPU.
This figure shows the four major components in the Central Processing Unit: the ALU, the
set of registers, the Control Unit, and the bus structure. The Control Unit issues signals to the
ALU that cause it to operate on input data and produce output data, which is possibly copied
back into one of the registers.
The control unit for this very simple ALU will issue four discrete control signals.
and the ALU takes the logical AND of B1 and B2
or the ALU takes the logical OR of B1 and B2
not the ALU takes the logical NOT of B1
add the ALU adds the contents of B1 and B2.
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The Arithmetic Logic Unit We now consider the ALU (Arithmetic Logic Unit) of the CPU (Central Processor Unit) of the computer and show how it is built from the circuits that we have previously considered. We shall begin with a very simple ALU, with a limited set of operations that include three Boolean operators (AND, OR, and NOT), simple transfer operations, and addition. The reader will note that three of the above operations (AND, OR, and addition) are dyadic ; that is, they require two arguments and produce one output. To accommodate this fact, all modern arithmetic logic units are constructed with two input busses and one output bus. Operations, such as W = X + Y + Z (adding three arguments) are always broken down into a sequence of dyadic operations in order to avoid great complexity in the CPU. The standard symbol for an ALU is shown in the figure below. The naming of the three busses is this author’s own notation, though similar to that used by other authors. Flow is from top to bottom; B1 and B2 are the input busses, and B3 is the output bus. As an aside at this point, we note that the three–bus ALU dictates a CPU with at least three internal busses, which are separate from the system bus that connects the CPU to memory and I/O devices. The figure below shows a rough view of the CPU. This figure shows the four major components in the Central Processing Unit: the ALU, the set of registers, the Control Unit, and the bus structure. The Control Unit issues signals to the ALU that cause it to operate on input data and produce output data, which is possibly copied back into one of the registers. The control unit for this very simple ALU will issue four discrete control signals. and the ALU takes the logical AND of B1 and B or the ALU takes the logical OR of B1 and B not the ALU takes the logical NOT of B add the ALU adds the contents of B1 and B2.

Logical Functions of the ALU We begin with an implementation of the logical functions. The main reason for this is that the processing of each bit can be considered separately. Suppose that we are dealing with 32–bit words. Each of the three busses will have 32 lines, one for each bit in the registers. The lines in bus B1 will be labeled as B1 31 though B1 0 with bit K being B1K. Busses B2 and B3 will be labeled in a similar manner. The reader should remember that the logical operations are bitwise implemented as the single bit Boolean operations discussed earlier. Thus, were we to have two 8–bit values X and Y. X = 0100 0110 X = 0100 0110 Y = 0111 1010 Y = 0111 1010 Y = 0111 1010 OR 0111 1110 AND 0100 0010 Not 1000 0101 The logical part of the ALU will consist of the following circuit, replicated 32 times. Note that these logical operations are bitwise, in that the output for bit K does not depend on the output of either bit (K – 1) or bit (K + 1). As a result, this circuit is the same for all 32 bits of the three busses. Note that the output of each of the three Boolean logic gates is connected to bus B3 via a tri–state buffer. This follows a common design practice that has two motivations.

  1. When the device is not active, there is no assertion of any signal on the output bus.
  2. The use of tri–states allows easy extension of the unit, just by simple addition of other gates also connected to the output bus via tri–states. The reader will note here a very common assumption in the design of any components to be used in the computer, particularly the CPU. That assumption is worth a paragraph. The control unit is assumed to work correctly. In this example, we have three control signals that are sent to the ALU from the Control Unit. Following his standard usage, your author has denoted these in bold lowercase font. They are “or” , “and” , and “not”. At any time, we must assume one of the 2 following situations.
  3. None of the control signals is asserted and the ALU is doing nothing.
  4. Exactly one of the control signals is asserted and the ALU is responding. If two or more of these control signals are asserted at the same time, all bets are off.