The Arithmetic Logic Unit
We now consider the ALU (Arithmetic Logic Unit) of the CPU (Central Processor Unit) of
the computer and show how it is built from the circuits that we have previously considered.
We shall begin with a very simple ALU, with a limited set of operations that include three
Boolean operators (AND, OR, and NOT), simple transfer operations, and addition.
The reader will note that three of the above operations (AND, OR, and addition) are dyadic;
that is, they require two arguments and produce one output. To accommodate this fact, all
modern arithmetic logic units are constructed with two input busses and one output bus.
Operations, such as W = X + Y + Z (adding three arguments) are always broken down into a
sequence of dyadic operations in order to avoid great complexity in the CPU.
The standard symbol for an ALU is shown in the figure below. The naming of the three
busses is this author’s own notation, though similar to that used by other authors. Flow is
from top to bottom; B1 and B2 are the input busses, and B3 is the output bus.
As an aside at this point, we note that the three–bus ALU dictates a CPU with at least three
internal busses, which are separate from the system bus that connects the CPU to memory
and I/O devices. The figure below shows a rough view of the CPU.
This figure shows the four major components in the Central Processing Unit: the ALU, the
set of registers, the Control Unit, and the bus structure. The Control Unit issues signals to the
ALU that cause it to operate on input data and produce output data, which is possibly copied
back into one of the registers.
The control unit for this very simple ALU will issue four discrete control signals.
and the ALU takes the logical AND of B1 and B2
or the ALU takes the logical OR of B1 and B2
not the ALU takes the logical NOT of B1
add the ALU adds the contents of B1 and B2.
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