Test Pattern Validation User Guide - Lecture Notes | ECE 128, Exams of Electrical and Electronics Engineering

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TetraMAX®

Test Pattern Validation User

Guide

Version W-2004.12, December 2004

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Copyright Notice and Proprietary Information Copyright © 2004 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Synopsys, Inc., or as expressly provided by the license agreement. Right to Copy Documentation The license agreement with Synopsys permits licensee to make copies of the documentation for its internal use only. Each copy shall include all copyrights, trademarks, service marks, and proprietary rights notices, if any. Licensee must assign sequential numbers to all copies. These copies shall contain the following legend on the cover page: “This document is duplicated with the permission of Synopsys, Inc., for the exclusive use of __________________________________________ and its employees. This is copy number __________.”

Destination Control Statement All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader’s responsibility to determine the applicable regulations and to comply with them. Disclaimer SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Registered Trademarks (®) Synopsys, AMPS, Arcadia, C Level Design, C2HDL, C2V, C2VHDL, Cadabra, Calaveras Algorithm, CATS, COSSAP, CSim, DelayMill, Design Compiler, DesignPower, DesignWare, EPIC, Formality, HSPICE, Hypermodel, I, iN-Phase, InSpecs, in-Sync, Leda, MAST, Meta, Meta-Software, ModelAccess, ModelTools, NanoSim, OpenVera, PathMill, Photolynx, Physical Compiler, PowerMill, PrimeTime, RailMill, Raphael, RapidScript, Saber, SiVL, SmartLogic, SNUG, SolvNet, Stream Driven Simulator, Superlog, System Compiler, Testify, TetraMAX, TimeMill, TMA, VCS, Vera, and Virtual Stepper are registered trademarks of Synopsys, Inc. Trademarks (™) abraCAD, abraMAP, Active Parasitics, AFGen, Apollo, Apollo II, Apollo-DPII, Apollo-GA, ApolloGAII, Astro, Astro-Rail, Astro- Xtalk, Aurora, AvanTestchip, AvanWaves, BCView, Behavioral Compiler, BOA, BRT, Cedar, ChipPlanner, Circuit Analysis, Columbia, Columbia-CE, Comet 3D, Cosmos, CosmosEnterprise, CosmosLE, CosmosScope, CosmosSE, Cyclelink, Davinci, DC Expert, DC Expert Plus , DC Professional, DC Ultra, DC Ultra Plus, Design Advisor, Design Analyzer, Design Vision, DesignerHDL, DesignTime, DFM-Workbench, DFT Compiler, Direct RTL, Direct Silicon Access, Discovery, DW8051, DWPCI, Dynamic-Macromodeling, Dynamic Model Switcher, ECL Compiler, ECO Compiler, EDAnavigator, Encore, Encore PQ, Evaccess, ExpressModel, Floorplan Manager, Formal Model Checker, FoundryModel, FPGA Compiler II, FPGA Express , Frame Compiler, Galaxy, Gatran, HDL Advisor, HDL Compiler, Hercules, Hercules-Explorer, Hercules-II, Hierarchical Optimization Technology, High Performance Option, HotPlace, HSPICE-Link, iN-Tandem, Integrator, Interactive Waveform Viewer, i-Virtual Stepper, Jupiter, Jupiter-DP, JupiterXT, JupiterXT-ASIC, JVXtreme, Liberty, Libra-Passport, Library Compiler, Libra-Visa, Magellan, Mars, Mars-Rail, Mars-Xtalk, Medici, Metacapture, Metacircuit, Metamanager, Metamixsim, Milkyway, ModelSource, Module Compiler, MS-3200, MS-3400, Nova Product Family, Nova-ExploreRTL, Nova-Trans, Nova-VeriLint, Nova-VHDLlint, Optimum Silicon, Orion_ec, Parasitic View, Passport, Planet, Planet-PL, Planet-RTL, Polaris, Polaris-CBS, Polaris-MT, Power Compiler, PowerCODE, PowerGate, ProFPGA, Progen, Prospector, Proteus OPC, Protocol Compiler, PSMGen, Raphael-NES, RoadRunner, RTL Analyzer, Saturn, ScanBand, Schematic Compiler, Scirocco, Scirocco-i, Shadow Debugger, Silicon Blueprint, Silicon Early Access, SinglePass-SoC, Smart Extraction, SmartLicense, SmartModel Library, Softwire, Source-Level Design, Star, Star-DC, Star-MS, Star-MTB, Star-Power, Star-Rail, Star-RC, Star-RCXT, Star-Sim, Star-SimXT, Star-Time, Star-XP, SWIFT, Taurus, Taurus-Device, Taurus-Layout, Taurus-Lithography, Taurus-OPC, Taurus-Process, Taurus-Topography, Taurus-Visual, Taurus-Workbench, TimeSlice, TimeTracker, Timing Annotator, TopoPlace, TopoRoute, Trace-On-Demand, True-Hspice, TSUPREM-4, TymeWare, VCS Express, VCSi, Venus, Verification Portal, VFormal, VHDL Compiler, VHDL System Simulator, VirSim, and VMC are trademarks of Synopsys, Inc. Service Marks (SM) MAP-in, SVP Café, and TAP-in are service marks of Synopsys, Inc.

SystemC is a trademark of the Open SystemC Initiative and is used under license. ARM and AMBA are registered trademarks of ARM Limited. All other product or company names may be trademarks of their respective owners.

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Contents

What’s New in This Release............................................. xvi Audience............................................................ xvi Related Publications................................................... xvi Conventions......................................................... xvii Customer Support..................................................... xviii

1. Introduction

Verilog DPV Testbench Overview........................................ 3 TetraMAX Pattern Format Overview...................................... 3 Write Verilog........................................................ 4 Write STIL...................................................... 5 Design to Test Validation Flow........................................... 6 PowerFault Overview.................................................. 8 Installation.......................................................... 9 Specifying the Location for TetraMAX Installation...................... 10

2. Using Verilog DPV Testbench

Licenses............................................................ 15 Overview........................................................... 15

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• Preparing Simulators for Verilog DPV Testbench
  • Synopsys VCS
    • Zero-Delay Simulation Considerations
  • Cadence NC-Verilog®
    • Running ncverilog
  • Cadence Verilog-XL®
    • Running verilogxl
  • Model Technology ModelSim®
  • Optimizing PLI Task Access
• Using Verilog DPV Testbench with TetraMAX
  • Specifying Serial/Parallel Simulation in TetraMAX
  • Specifying Serial/Parallel Simulation in Compilation
    • Enabling Parallel-Scan Access
  • Modifying Serial and Parallel Options
• Using Verilog DPV Testbench with BSD Compiler.
• Using Verilog DPV Testbench with SoCTest
• Using Verilog DPV Testbench with Memory BIST
• Mapping Between STIL Signals and Verilog Constructs.
• Running Verilog DPV Testbench
  • Threads.
  • Vector Counts.
  • VCS Simulation Output
• Simulation-to-STIL Output Checking
• PLI Task Functions
• Message Examples
• Summary of Specific STIL Issues
  • Single-Cycle Capture Procedures and Bidirectional Signals.
  • Multi-Cycle Capture Procedures and Bidirectional Signals
  • Bidirectional Signals and Load-Unload Procedures
  • Missing States on Primary Outputs
  • Empty Waveform Definition
  • STIL-nnn Error Messages
• Verilog DPV Limitations
• Verilog DPV Parallel-BIST Accelerated Simulation vii
  • Creating a New STIL Format
  • Enhancing the STIL Format.
  • Example STIL Data Modifications
• Introduction 3. Verilog DPV Parallel-BIST Accelerated Simulation
• Creating a New STIL Format
• Enhancing the STIL Format
• Example STIL Data Modifications.
• Limitations
• Introduction 4. Troubleshooting Verilog DPV
• Troubleshooting Errors
  • STIL Signal Not Found
  • Incomplete STIL Files
  • STIL Initialization Error
• Troubleshooting Miscompares
• Miscompare Messages
• Miscompare Message
• Miscompare Message
• Miscompare Message
• Miscompare Message
• What to do First When a Failure Occurs
• Resolving the First Failure
• Miscompare Fingerprints
• Expected versus Actual States
• Current Waveform Table
• Labels and Calling Stack
• Additional Troubleshooting Help
• Trace Debugging
• Adding More Fingerprints viii
• Error from STILDPV_done
• Troubleshooting Verilog DPV and VCS Error Messages.
• Chain Not Found Error
• Workaround
• Undefined System Task Error.
• Workaround
• Output Mismatch Error.
  • Workaround
• Troubleshooting Verilog DPV and NC Verilog Error Messages
• Access Error
• Workaround
• SYSTEM ERROR: VPI LOADLB - Workaround
• STIL Signal Error
• Workaround
  • Contact Cadence Error
• Verilog DPV Parallel-BIST Accelerated Simulation
  • Creating a New STIL Format
  • Enhancing the STIL Format.
  • Example STIL Data Modifications
• SoCBIST DBIST / XDBISTVerilog DPV Debug
• STILDPV Testbench Structure
• Adding a $monitor statement to the Verilog testbench.
• Verilog DPV Simulation Sequence.
• Verilog DPV Simulation Sequence.
• Verilog DPV Recommendations.
• PowerFault Simulation Technology 5. PowerFault Simulation
• IDDQ Testing Flows.
  • IDDQ Test-Pattern Generation.
  • IDDQ Strobe Selection From an Existing Pattern Set
• Licensing ix
• Preparing Simulators for PowerFault IDDQ 6. Verilog Simulation with PowerFault
  • Synopsys VCS
  • Cadence NC-Verilog
    • Running ncverilog
  • Cadence Verilog-XL
    • Running verilogxl
  • Model Technology ModelSim
• PowerFault PLI Tasks.
• PLI Task Command Summary Table
• PLI Task Command Reference. x
  • Conventions
    • Special-Purpose Characters.
    • Module Instances and Entity Models
    • Cell Instances
    • Port and Terminal References
  • Simulation Setup Commands.
    • dut
    • output.
    • ignore.
    • io
    • statedep_float
    • measure
    • verb
  • Leaky State Commands
    • allow
    • disable SepRail
    • disallow
  • Fault Seeding Commands
    • seed SA
    • seed B
    • scope
    • read_bridges
    • read_tmax
    • read_verifault
    • read_zycad.
  • Fault Seed Exclusion Command
    • exclude
  • Fault Model Commands.
    • model SA.
    • model B
  • Strobe Commands
    • strobe_try.
    • strobe_force
    • strobe_limit
    • cycle
  • Circuit Examination Commands
    • status
    • summary
• Fault Models 7. Faults and Fault Seeding
  • Fault Models in TetraMAX
  • Fault Models in PowerFault.
    • Stuck-At Faults
    • Bridging Faults
• Fault Seeding
  • Seeding From a TetraMAX Fault List
  • Seeding From an External Fault List
  • PowerFault-Generated Seeding
• Options for PowerFault-Generated Seeding.
  • Stuck-At Fault Model Options.
    • Default Stuck-At Fault Seeding
    • all_mods
    • cell_mods
    • leaf_mods
    • prims
    • seed_inside_cells
  • Bridging Faults.
    • cell_ports
    • fet_terms
    • gate_IN2IN
    • gate_IN2OUT
    • vector
    • seed_inside_cells
• Overview of IDDQPro 8. PowerFault Strobe Selection
• Invoking IDDQPro xii
  • Strobe Selection Options
    • -strb_lim
    • -cov_lim
    • -strb_set
    • -strb_unset
    • -strb_all
  • Report Configuration Options
    • -prnt_fmt
    • -prnt_nofrpt
    • -prnt_full, -prnt_times, and -path_sep.
    • -ign_uncov.
  • Log File Option
  • Interactive Option
• Interactive Strobe Selection
  • cd
  • desel
  • exec
  • help.
  • ls
  • prc
  • prf.
  • prs.
  • quit
  • reset
  • sela
  • selm
  • selall
• Strobe Reports
  • Fault Coverage Calculation
    • Faults Detected by Previous Runs.
    • Undetected Faults Excluded From Simulation
    • Faults Detected at Uninitialized Nodes
  • Adding More Strobes
  • Deleting Low-Coverage Strobes
• Fault Reports.
  • TetraMAX Format
  • Verifault Format
  • Zycad Format
  • Listing Seeded Faults
• PowerFault Verification and Strobe Selection 9. Using PowerFault Technology
  • Verifying TetraMAX IDDQ Patterns for Quiescence
  • Selecting Strobes in TetraMAX Stuck-At Patterns
  • Selecting Strobe Points in Externally Generated Patterns
• Testbenches for IDDQ Testability
  • Separate the Testbench From the Device Under Test
  • Drive All Input Pins to 0 or 1.
  • Try Strobes After Scan Chain Loading
  • Include a CMOS Gate in the Testbench for Bidirectional Pins
  • Model the Load Board
  • Mark the I/O Pins.
  • Minimize High-Current States
  • Maximize Circuit Activity
• Combining Multiple Verilog Simulations.
• Improving Fault Coverage
  • Determine Why the Chip Is Leaky
  • Evaluate Solutions
    • Use the allow Command
    • Configure the Verilog Testbench
    • Configure the Verilog Models
• Floating Nodes and Drive Contention
  • Floating Node Recognition
    • State-Dependent Floating Nodes.
    • Configuring Floating Node Checks.
    • Floating Node Reports
    • Nonfloating Nodes
  • Drive Contention Recognition
• Status Command Output.
  • Leaky Reasons
  • Nonleaky Reasons
  • Driver Information
• Behavioral and External Models
  • Disallowing Specific States
  • Disallowing Global States
• Multiple Power Rails
• Testing I/O and Core Logic Separately

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10. Strobe Selection Tutorial Simulation and Strobe Selection.......................................... 226 Examine the Verilog File........................................... 226 Run the doit Script................................................ 227 Examine the Output Files........................................... 228 Interactive Strobe Selection............................................. 230 Select Strobes Automatically........................................ 230 Select All Strobes................................................. 232 Select Strobes Manually............................................ 233 Cumulative Fault Selection......................................... 235 11. Interfaces to Fault Simulators Verifault Interface..................................................... 238 Zycad Interface....................................................... 239 12. Iterative Simulation Sample Procedure..................................................... 242

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About This Manual What’s New in This Release

What’s New in This Release

Information about new features, enhancements, and changes; known problems and limitations; and resolved Synopsys Technical Action Requests (STARs) is available in the TetraMAX ATPG Release Notes in SolvNet. To see the TetraMAX ATPG Release Notes,

1. Go to the Synopsys Web page at http://www.synopsys.com and click SolvNet.
2. If prompted, enter your user name and password. (If you do not have a Synopsys user name and password, follow the instructions to register with SolvNet.)
3. Click Release Notes in the Main Navigation section, find the Release Notes, then open the TetraMAX ATPG Release Notes.

Audience

This manual and the associated products are intended for the following users:

• TetraMAX ATPG users who generate STIL-formatted test patterns. Users are assumed to be familiar with STIL, ATPG testing, and CMOS circuitry.
• TetraMAX ATPG users who are using, or thinking about using, IDDQ testing techniques to improve product quality. Users are assumed to have some familiarity with ATPG testing and CMOS circuitry.
• SoCBIST users who need to validate STIL test patterns for cores, either pre- or post-insertion into an SoC.

Related Publications

For additional information about Verilog DPV testbench and PowerFault, see

• Synopsys Online Documentation (SOLD), which is included with the software
• Documentation on the Web, which is available through SolvNet at http:// solvnet.synopsys.com.
• The Synopsys MediaDocs Shop, from which you can order printed copies of Synopsys documents, at http://solvnet.synopsys.com/modServlet You might also want to refer to the documentation for the following related Synopsys products:

xvii

About This Manual Conventions

• TetraMAX ATPG
• VCS (Verilog Simulator)

Conventions

The following conventions are used in Synopsys documentation. Table 1 Notational Conventions

Convention Description

Courier Indicates command syntax.

Courier italic Indicates a user-defined value in Synopsys syntax,

such as object_name. (A user-defined value that

is not Synopsys syntax, such as a user-defined value

in a Verilog or VHDL statement, is indicated by

regular text font italic.)

Courier bold Indicates user input—text you type verbatim—in

Synopsys syntax and examples. (User input that is

not Synopsys syntax, such as a user name or

password you enter in a GUI, is indicated by regular

text font bold.)

[ ] Denotes optional parameters, such as

pin1 [ pin2 ... pinN ]

| Indicates a choice among alternatives, such as

low | medium | high

(This example indicates that you can enter one of

three possible values for an option:

low, medium, or high.)

_ Connects terms that are read as a single term by the

system, such as

set_annotated_delay

Control-c Indicates a keyboard combination, such as holding

down the Control key and pressing c.

\ Indicates a continuation of a command line.

/ Indicates levels of directory structure.

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About This Manual Customer Support

• Call (650) 584-4200 from Canada.
• Find other local support center telephone numbers at http://www.synopsys.com/support/support_ctr.

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About This Manual Customer Support