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System Buses - Processor Architecture and Microprogramming - Lecture Slides, Slides of Computer Architecture and Organization

During the course of work of the microprogramming, we learn the core of the programming. The main points disucss in these lecture slides are:System Buses, Program Concept, Sequence of Steps, Function of Control Unit, Temporary Storage of Code, Computer Components, Instruction Cycle, Fetch Cycle, Instruction Register, Example of Program Execution

Typology: Slides

2012/2013

Uploaded on 04/24/2013

banani
banani 🇮🇳

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Chapter 3
System Buses
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Chapter 3

System Buses

Program Concept

  • Hardwired systems are inflexible
  • General purpose hardware can do different tasks, given correct control signals
  • Instead of re-wiring, supply a new set of control signals

Function of Control Unit

  • For each operation a unique code is provided —e.g. ADD, MOVE
  • A hardware segment accepts the code and issues the control signals
  • We have a computer!

Components

  • The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit
  • Data and instructions need to get into the system and results out —Input/output
  • Temporary storage of code and results is needed —Main memory
  • Secondary storage are also required

Instruction Cycle

  • Two steps: —Fetch —Execute

Fetch Cycle

  • Program Counter (PC) holds address of next instruction to fetch
  • Processor fetches instruction from memory location pointed to by PC
  • Increment PC —Unless told otherwise
  • Instruction loaded into Instruction Register (IR)
  • Processor interprets instruction and performs required actions

Example of Program Execution

Instruction Cycle - State Diagram

Program Flow Control

Interrupt Cycle

  • Added to instruction cycle
  • Processor checks for interrupt — Indicated by an interrupt signal
  • If no interrupt, fetch next instruction
  • If interrupt pending: — Suspend execution of current program — Save context — Set PC to start address of interrupt handler routine — Process interrupt — Restore context and continue interrupted program

Instruction Cycle (with Interrupts) - State Diagram

Multiple Interrupts

  • Disable interrupts —Processor will ignore further interrupts whilst processing one interrupt —Interrupts remain pending and are checked after first interrupt has been processed —Interrupts handled in sequence as they occur
  • Define priorities —Low priority interrupts can be interrupted by higher priority interrupts —When higher priority interrupt has been processed, processor returns to previous interrupt

Multiple Interrupts – Nested

Time Sequence of Multiple Interrupts