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SRAM: Static Random Access Memory, Summaries of Electrical and Electronics Engineering

A comprehensive overview of sram (static random access memory), a type of volatile memory commonly used in computer systems. It covers the architecture of sram, including the sram cell design, decoders, column circuitry, and support for multiple ports. The document also discusses serial access memories, such as shift registers, tapped delay lines, and fifo/lifo queues, which are often used in conjunction with sram. The detailed technical explanations, accompanied by circuit diagrams and waveforms, make this document a valuable resource for students and professionals interested in understanding the design and implementation of sram and related memory technologies. Part of a larger textbook on cmos vlsi design, providing a solid foundation in the principles and practices of integrated circuit design.

Typology: Summaries

2023/2024

Uploaded on 04/28/2024

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Lecture 19:
SRAM
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Lecture 19:

SRAM

Outline

 (^) Memory Arrays  (^) SRAM Architecture

  • (^) SRAM Cell
  • (^) Decoders
  • (^) Column Circuitry
  • (^) Multiple Ports  (^) Serial Access Memories

Array Architecture

 2 n^ words of 2m^ bits each  (^) If n >> m, fold by 2k^ into fewer rows of more columns  (^) Good regularity – easy to design  (^) Very high density if good cells are used

12T SRAM Cell

 (^) Basic building block: SRAM Cell

  • (^) Holds one bit of information, like a latch
  • (^) Must be read and written  (^) 12-transistor (12T) SRAM cell
  • (^) Use a simple latch connected to bitline
  • (^) 46 x 75  unit cell bit write write_b read read_b

SRAM Read

 (^) Precharge both bitlines high  (^) Then turn on wordline  (^) One of the two bitlines will be pulled down by the cell  (^) Ex: A = 0, A_b = 1

  • (^) bit discharges, bit_b stays high
  • (^) But A bumps up slightly  (^) Read stability
  • (^) A must not flip
  • (^) N1 >> N bit bit_b N N P A P N N A_b word

0 100 200 300 400 500 600 time (ps) word bit A A_b (^) bit_b

SRAM Write

 (^) Drive one bitline high, the other low  (^) Then turn on wordline  (^) Bitlines overpower cell with new value  (^) Ex: A = 0, A_b = 1, bit = 1, bit_b = 0

  • (^) Force A_b low, then A rises high  (^) Writability
  • (^) Must overpower feedback inverter
  • (^) N2 >> P time (ps) word A A_b bit_b

0 100 200 300 400 500 600 700 bit bit_b N N P A P N N A_b word

SRAM Column Example

Read Write H H SRAM Cell word_q bit_v1f bit_b_v1f out_b_v1r out_v1r  1  2 word_q bit_v1f out_v1r  2 More Cells Bitline Conditioning  2 More Cells SRAM Cell word_q bit_v1f bit_b_v1f data_s write_q Bitline Conditioning

SRAM Layout

 (^) Cell size is critical: 26 x 45  (even smaller in industry)  (^) Tile cells sharing V DD , GND, bitline contacts VDD GND BIT BIT_B GND WORD Cell boundary

Commercial SRAMs

 (^) Five generations of Intel SRAM cell micrographs

  • (^) Transition to thin cell at 65 nm
  • (^) Steady scaling of cell area

Decoders

 (^) n:2n^ decoder consists of 2n^ n-input AND gates

  • (^) One needed for each row of memory
  • (^) Build AND from NAND or NOR gates Static CMOS Pseudo-nMOS word word word word A1 A A word A0 (^1 ) 1/ 2 4 8 16 word A A 1 1 1 1 4 word0 8 word word word A1 A

Large Decoders

 (^) For n > 4, NAND gates become slow

  • (^) Break large gates into multiple smaller gates word word word word word A3 A2 A1 A

Predecoding

 (^) Many of these gates are redundant

  • (^) Factor out common gates into predecoder
  • (^) Saves area
  • (^) Same path effort A A A A word word word word word 1 of 4 hot predecoded lines predecoders

Bitline Conditioning

 (^) Precharge bitlines high before reads  (^) Equalize bitlines to minimize voltage difference when using sense amplifiers  bit bit_b  bit bit_b

Sense Amplifiers

 (^) Bitlines have many cells attached

  • (^) Ex: 32-kbit SRAM has 128 rows x 256 cols
  • (^) 128 cells on each bitline  (^) t pd

 (C/I) V

  • (^) Even with shared diffusion contacts, 64C of diffusion capacitance (big C)
  • (^) Discharged slowly through small transistors (small I)  (^) Sense amplifiers are triggered on small voltage swing (reduce V)