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A comprehensive overview of sram (static random access memory), a type of volatile memory commonly used in computer systems. It covers the architecture of sram, including the sram cell design, decoders, column circuitry, and support for multiple ports. The document also discusses serial access memories, such as shift registers, tapped delay lines, and fifo/lifo queues, which are often used in conjunction with sram. The detailed technical explanations, accompanied by circuit diagrams and waveforms, make this document a valuable resource for students and professionals interested in understanding the design and implementation of sram and related memory technologies. Part of a larger textbook on cmos vlsi design, providing a solid foundation in the principles and practices of integrated circuit design.
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(^) Memory Arrays (^) SRAM Architecture
2 n^ words of 2m^ bits each (^) If n >> m, fold by 2k^ into fewer rows of more columns (^) Good regularity – easy to design (^) Very high density if good cells are used
(^) Basic building block: SRAM Cell
(^) Precharge both bitlines high (^) Then turn on wordline (^) One of the two bitlines will be pulled down by the cell (^) Ex: A = 0, A_b = 1
0 100 200 300 400 500 600 time (ps) word bit A A_b (^) bit_b
(^) Drive one bitline high, the other low (^) Then turn on wordline (^) Bitlines overpower cell with new value (^) Ex: A = 0, A_b = 1, bit = 1, bit_b = 0
0 100 200 300 400 500 600 700 bit bit_b N N P A P N N A_b word
Read Write H H SRAM Cell word_q bit_v1f bit_b_v1f out_b_v1r out_v1r 1 2 word_q bit_v1f out_v1r 2 More Cells Bitline Conditioning 2 More Cells SRAM Cell word_q bit_v1f bit_b_v1f data_s write_q Bitline Conditioning
(^) Cell size is critical: 26 x 45 (even smaller in industry) (^) Tile cells sharing V DD , GND, bitline contacts VDD GND BIT BIT_B GND WORD Cell boundary
(^) Five generations of Intel SRAM cell micrographs
(^) n:2n^ decoder consists of 2n^ n-input AND gates
(^) For n > 4, NAND gates become slow
(^) Many of these gates are redundant
(^) Precharge bitlines high before reads (^) Equalize bitlines to minimize voltage difference when using sense amplifiers bit bit_b bit bit_b
(^) Bitlines have many cells attached