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Homework Assignment # This assigment is intended as a run through the Quick VHDL system. The commands relevant to this VHDL system are: (on the Red Hat Systems)
vlib library_name this command creates a library for the analyzed designs. (you will need a library called “work”)
vcom design_file.vhdl the VHDL compile command vcom -source design_file.vhdl will print the source line and then the error message
vdel design_unit deletes the design unit from the library
vsim no arguments - starts up simulator - allows you to select library and design unit. The control window also allows you to compile You can do everything from this window or use the specific Commands. You can even bring up a text editor to enter your VHDL.
vdir [ -lib <library_name> ] [<entity_name>] lists contents of a library
vmap [<logical_name>] [] defines a mapping between a logical library and a library directory qhmap work ~/ee762/pr_step2_lib
On the PC systems: Under the FILE menu choose the Change Directory selection. When the popup appears navigate to the directory where you will be doing the work for this course.
Under the FILE menu choose the Source Directory selection. When the popup appears choose BROWSE and navigate to where your source files will be located.
The assignment STEP 1) In a terminal window on the Red Hat Systems do the following: (--Bring up a terminal window. NOT required on PC systems.)
Insure that you have a path set to access the mentor tools. Execute
echo $PATH In response to this command you should get PATH=/opt • • • with /opt/local/mentormaster/modeltech/bin somewhere in the path
> printenv | grep MGC In response to this command you should get an appropriate response for your account.
If you do not get these (you may get more but that is ok), then add the following to your .login file (at a point after the “setenv PATH ...”)
source /opt/local/mentormaster/SETUP.MODELSIM
STEP 2) Create a directory for your work in this class and possibly even subdirectories for homework and one for the project steps. Possibly ece762 and hw as the subdirectory. Change directory to that directory and create a file with the following contents: (the remainder of this handout assumes you name the file, hw1.vhdl) You can use a text editor (be sure to save as plain text. You can use the editor within ModelSim on both the PC and LINUX systems.
ENTITY first_test IS END first_test; ARCHITECTURE one OF first_test IS SIGNAL phi1, phi2 : BIT; BEGIN PROCESS BEGIN WAIT FOR 10 NS; phi1 <= ’0’; phi2 <= ’1’; WAIT FOR 10 NS; phi1 <= ’1’; phi2 <= ’0’; END PROCESS; END one;
The editor in the Modeltech GUI is under FILE- -> NEW - -> Source - ->VHDL
STEP 3) In the directory for your work and contianing the file you just entered, you need to create a VHDL library. To do this execute -- start up the system
vsim& on LINUX systems or choose and click on PCs Once MODELSIM is running Under the file pulldown choose NEWLibrary A popup will ask for the Library name and the physical name – by default they are both “work”
Or from the command line you could have issued the command (on LINUX) > vlib work
Then you can compile your design (this can also be done from the simulator window when you start it but try the command from the command line)
> vcom hw1.vhdl
In the GUI choose COMPILE- -> COMPILE
A popup will allow you to choose hw1.vhdl for compilation.
NOTE: If you compile the unit from the command line it will not appear in library work until you (re)state the simulator.
NOTE: You can accomplish everything from the GUI window. To create a new library the menu selection is on FileNewLibrary… (Note that you do want a library called work) To create and edit a new source file of VHDL code it is FileNewVHDL (Note the simulator also works with Verilog and System C) (This is actually a very nice editor for entering VHDL code)
