Download Solved Quiz 3 for Digital Design Fundamentals - Fall 2011 | CSE 120 and more Quizzes Computer Science in PDF only on Docsity!
CSE/EEE120 Fall 2011 Group/Team Quiz #
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You have 30 minutes to complete and turn in this quiz. This quiz is worth 100 points. Please read questions carefully and provide the answers to each part of the design question. Show all of your work. Good luck!
Using the Moore machine design methodology, design a circuit that counts both upwards and downwards in the following manner:
Input x = 1 2, 4, 6, 2, 4, 6, … and so on. x = 0 6, 4, 2, 6, 4, 2, … and so on.
Assume that an external reset is available and that the flip-flops are positive edge-triggered devices with active-low reset inputs. An external reset should set the Moore machine to the output value of z = 2.
Show/draw the following components of your design:
(a) State description table (including binary assignments). (b) State transition diagram. (c) State transition table. (d) Appropriate Karnaugh maps and corresponding equations for an implementation using D or J-K flip-flops. (e) Final circuit schematic using D or J-K flip-flops.
The behavioral equation for a D flip-flop is : q* = D The behavioral equation for a J-K flip-flop is : q* = Jq' + K'q
(a) We first set up a state definition table, determining what states the flip-flops can be in:
In order to represent all three output conditions, we need to store three states. In binary representation this implies that we need two bits to store the state information, thus we need two flip-flops to implement our counter. One state (binary 0 0) is not being used.
(b) With this definition, we can complete the state transition diagram for the two different input conditions of x :
(c) Based on this state diagram, we can now set up our state transition table as follows:
The z column represents the output based on q 1 and q 0 in decimal format. Because it is a Moore machine, there is no dependence on x, thus the first four lines and the last four lines are identical. In order to obtain the z output in binary representation, we need three bit lines z 2 , z 1 and z 0. We only have two flip flops, but we can "generate" the correct output by wiring z 2 to q 1 , z 1 to q 0 and z 0 to 0 (shift-left).
State Definition Binary S 0 z = 1 0 1 S 1 z = 2 1 0 S 2 z = 3 1 1
x q 1 q 0 q 1 * q 0 * z z 2 z 1 z 0 0 0 0 X X X X X X 0 0 1 1 1 2 0 1 0 0 1 0 0 1 4 1 0 0 0 1 1 1 0 6 1 1 0 1 0 0 X X X X X X 1 0 1 1 0 2 0 1 0 1 1 0 1 1 4 1 0 0 1 1 1 0 1 6 1 1 0
S 2
S 1
S 0
(e) Using XOR gates, we can significantly simplify the schematic.
D C
S R
Q Q
DEV
D C
S R
Q Q
DEV
2
+5V
0 1
+5V 01
Reset
X
2
+5V
JS C K R
Q Q
DEV
JS C K R
Q Q
DEV
0 1
+5V
+5V 0 1
x
Reset
