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Instructions for designing a finite state machine (fsm) to calculate the factorial of a given number using an 8-bit datapath. The design process includes writing high-level pseudo-code, converting it to control words, drawing the state diagram, deriving the next-state table, and implementing the excitation and output equations. The fsm uses d flip-flops and has inputs for the number (n) and control signals.
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Use the datapath and functional operations shown in Figure 1 below to implement the following algorithm:
Input a number n and output the factorial of n , i.e. n! Assume that n is small and no overflow error results from the calculations.
Use D flip-flops for the FSM.
You need to do the following: a) Write the high-level pseudo-code to implement the algorithm. (2) b) Convert the pseudo-code to control words. (2) c) Draw the state-diagram for the control words. (2) d) Derive the next-state/implementation table. (2) e) Derive the excitation equations. (2) f) Derive the output equations. (2) g) Draw the complete FSM circuit. (2) h) Draw the circuit(s) that generates signals from the datapath for the FSM. (2)
15
Input
mux
1 0
WE WA^4 x^8 RAE RF RAA
RBE RBA
14 13- 11 10-
8 7-
Clk
5 4 3
0
IE
OE
ALU
ALU 2 ALU 1 ALU 0
A B
SH SH (^1) Shifter 0
2 1
(a)
Figure 1. 8-bit datapath with register file: (a) circuit; (b) ALU operations; (c) Shifter operations.
ALU 2 ALU 1 ALU 0 Operation 0 0 0 Pass through A 0 0 1 A AND B 0 1 0 A OR B 0 1 1 NOT A 1 0 0 A + B 1 0 1 A โ B 1 1 0 A + 1 1 1 1 A โ 1
(b)
SH 1 SH 0 Operation 0 0 Pass through 0 1 Shift left 1 0 Shift right 1 1 Rotate right
(c)
Answer
a)
b) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 State IE WE WA RAE RAA RBE RBA ALU SH OE Comment
(^1 1 1 00 0) รร 0 รร รรร รร 0 input n 2 0 1 01 0 00 0 00 101 00 0 fac = 0 (^3 0 1 01 1 01 0) รร 110 00 0 fac ++ (^4 0 1 10 1 00 0) รร 000 00 0 count = n (^5 0 1 11 1 01 0) รร 000 00 0 add = fac 6 0 1 01 1 01 1 11 100 00 0 fac = fac + add (^7 0 1 10 1 10 0) รร 111 00 0 count = count โ 1 (^8 0 1 00 1 00 0) รร 111 00 0 n = n โ 1 (^9 0 0) รร 1 01 0 รร 000 00 1 output fac
c)
d) We can use one signal for both ( n > 1) and ( count > 1) since the comparator taps into the same point in the datapath and when that signal is needed, the value for the corresponding variable is available at that point.
Next State Current State Start , ( n_count >1) Q 3 Q 2 Q 1 Q 0 00 01 10 11 0000 0000 0000 0001 0001 0001 0010 0010 0010 0010 0010 0011 0011 0011 0011 0011 0100 0100 0100 0100 0100 0101 0101 0101 0101 0101 0110 0110 0110 0110 0110 1000 0111 1000 0111 0111 0110 0110 0110 0110 1000 1001 0100 1001 0100 1001 0000 0000 0000 0000
e) Note that the equations are not necessarily minimized. There can be other solutions.
D 3 = Q 3 'Q 2 Q 1 Q 0 ' Start' ( n_count >1) ' + Q 3 'Q 2 Q 1 Q 0 ' Start ( n_count >1) ' + Q 3 Q 2 'Q 1 'Q 0 ' Start' ( _n- count >1) ' + Q 3 Q 2 'Q 1 'Q 0 ' Start ( n_count >1) ' = Q 3 'Q 2 Q 1 Q 0 ' ( n_count >1) ' + Q 3 Q 2 'Q 1 'Q 0 ' ( n_count >1) '
D 2 = Q 3 'Q 2 Q 1 ' + Q 3 'Q 2 ( n_count >1) + Q 3 'Q 2 'Q 1 Q 0 + Q 3 'Q 2 Q 1 Q 0 = Q 3 'Q 2 Q 1 ' + Q 3 'Q 2 ( n_count >1) + Q 3 'Q 1 Q 0
D 1 = Q 3 'Q 2 'Q 1 'Q 0 + Q 3 'Q 2 'Q 1 Q 0 ' + Q 3 'Q 2 Q 1 'Q 0 + Q 3 'Q 2 Q 1 Q 0 + Q 3 'Q 2 Q 1 Q 0 ' ( n_count >1) = Q 3 'Q 2 'Q 1 'Q 0 + Q 3 'Q 2 'Q 1 Q 0 ' + Q 3 'Q 2 Q 0 + Q 3 'Q 2 Q 1 Q 0 ' ( n_count >1)
D 0 = Q 3 'Q 2 'Q 1 'Q 0 'start + Q 3 'Q 2 'Q 1 Q 0 ' + Q 3 'Q 2 Q 1 'Q 0 ' + Q 3 'Q 2 Q 1 Q 0 ' ( n_count >1) + Q 3 Q 2 'Q 1 'Q 0 ' ( n_count >1) '
f) The output equations are obtained from b). Note that the equations are not necessarily minimized. There can be other solutions.
IE = Q 3 'Q 2 'Q 1 'Q 0 WE = ( Q 3 Q 2 'Q 1 'Q 0 ) ' WA 1 = Q 3 'Q 2 Q 1 'Q 0 ' + Q 3 'Q 2 Q 1 'Q 0 + Q 3 'Q 2 Q 1 Q 0 = Q 3 'Q 2 Q 1 ' + Q 3 'Q 2 Q 1 Q 0 WA 0 = Q 3 'Q 2 'Q 1 Q 0 ' + Q 3 'Q 2 'Q 1 Q 0 + Q 3 'Q 2 Q 1 'Q 0 + Q 3 'Q 2 Q 1 Q 0 ' = Q 3 'Q 2 'Q 1 + Q 3 'Q 2 Q 1 'Q 0 + Q 3 'Q 2 Q 1 Q 0 ' RAE = ( Q 3 'Q 2 'Q 1 'Q 0 + Q 3 'Q 2 'Q 1 Q 0 ' ) ' RAA 1 = Q 3 'Q 2 Q 1 Q 0 RAA 0 = Q 3 'Q 2 'Q 1 Q 0 + Q 3 'Q 2 Q 1 'Q 0 + Q 3 'Q 2 Q 1 Q 0 ' + Q 3 Q 2 'Q 1 'Q 0
g) I think I got the following correct โบ.
Clk
D 1
Q' 1
Q 1
Clk
D 2
Q' 2
Q 2
Clk
D 3
Q' 3
Q 3
Start
Clk
Clk
D 0
Q' 0
Q 0
Q 3 Q 2 Q 1 Q 0
( n_count> 1)
IE WE
RBE, RBA 1 , RBA 0
'0' SH 1 , SH 0
etc.