Docsity
Log inSign up
Docsity
Prepare for your exams
Prepare for your exams

Study with the several resources on Docsity

Earn points to download
Earn points to download

Earn points by helping other students or get them with a premium plan

Guidelines and tips
Guidelines and tips
Sell on Docsity
Sell on Docsity
Log inSign up

Prepare for your exams

Study with the several resources on Docsity

Find documents

Prepare for your exams with the study notes shared by other students like you on Docsity

Search Store documents

The best documents sold by students who completed their studies

Search through all study resources
Docsity AINEW

Summarize your documents, ask them questions, convert them into quizzes and concept maps

Explore questions

Clear up your doubts by reading the answers to questions asked by your fellow students

Earn points to download

Earn points by helping other students or get them with a premium plan

Share documents
download point icon20 Points

For each uploaded document

Answer questions
download point icon5 Points

For each given answer (max 1 per day)

All the ways to get free points
Get points immediately

Choose a premium plan with all the points you need

Study Opportunities

Choose your next study program

Get in touch with the best universities in the world. Search through thousands of universities and official partners

Community

Ask the community

Ask the community for help and clear up your study doubts

University Rankings

Discover the best universities in your country according to Docsity users

Free resources

Our save-the-student-ebooks!

Download our free guides on studying techniques, anxiety management strategies, and thesis advice from Docsity tutors

From our blog

Exams and Study
Go to the blog

solution of marris mano 5 edition, Study notes of Digital Electronics

Hemwati Nandan Bahuguna Garhwal UniversityDigital Electronics

it is solution manual for digital electronics book marris mano.

Typology: Study notes

2017/2018
On special offer
40 Points
Discount

Limited-time offer

Uploaded on 02/06/2018

ayushri-srivastva
ayushri-srivastva ๐Ÿ‡ฎ๐Ÿ‡ณ

2.5

(4)

2 documents

1 / 26

Toggle sidebar

This page cannot be seen from the preview

Don't miss anything!

bg1
!
Digital'Design'With'An'Introduction'to'the'Verilog'HDL'โ€“'Solution'Manual.!M.!Mano.!M.D.!Ciletti,!Copyright!2012,!!
All!rights!reserved.!
1!
SOLUTIONS MANUAL
!
!
DIGITAL'DESIGN'
WITH'AN'INTRODUCTION'TO'THE'VERILOG'HDL'
Fifth'Edition'
!
!
!
!
M.'MORRIS'MANO'
Professor'Emeritus'
California'State'University,'Los'Angeles'
'
MICHAEL'D.'CILETTI'
Professor'Emeritus'
'
University'of'Colorado,'Colorado'Springs'
'
rev'02/14/2012'
!
pf3
pf4
pf5
pf8
pf9
pfa
pfd
pfe
pff
pf12
pf13
pf14
pf15
pf16
pf17
pf18
pf19
pf1a
Discount

On special offer

Partial preview of the text

Download solution of marris mano 5 edition and more Study notes Digital Electronics in PDF only on Docsity!

Digital Design With An Introduction to the Verilog HDL โ€“ Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,

SOLUTIONS MANUAL

DIGITAL DESIGN

WITH AN INTRODUCTION TO THE VERILOG HDL

Fifth Edition

M. MORRIS MANO

Professor Emeritus

California State University, Los Angeles

MICHAEL D. CILETTI

Professor Emeritus

University of Colorado, Colorado Springs

rev 02/14/

Digital Design With An Introduction to the Verilog HDL โ€“ Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,

1.8 (a) Results of repeated division by 2 (quotients are followed by remainders): (b) Results of repeated division by 16:

Digital Design With An Introduction to the Verilog HDL โ€“ Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,

(b) 1800 โ†’ 01800 โ†’ 9 8199 (9s comp) โ†’ 98200 (10 comp)

  • CHAPTER
  • 1.1 Base-10:
    • Octal:
    • Hex: 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
    • Base- 12 14 15 16 17 18 19 1A 1 B
    1. 2 (a) 32,768 (b) 67,108,864 (c) 6,871,947,
    1. 3 (4310) 5 = 4 * 53 + 3 * 52 + 1 * 51 =
    • (198) 12 = 1 * 122 + 9 * 121 + 8 * 120 =
    • (435) 8 = 4 * 82 + 3 * 81 + 5 * 80 =
    • ( 345 ) 6 = 3 * 62 + 4 * 61 + 5 * 60 =
  • 1.4 16 - bit binary: 1111 1111_1111
    • Decimal equivalent: 216 - 1 = 65,535
    • Hexadecimal equivalent: FFFF
    • (a) 14/2 = (b + 4)/2 = 5, so b = 1. 5 Let b = base
    • (b) 54/4 = (5*b + 4)/4 = b + 3, so 5 * b = 52 โ€“ 4, and b =
    • (c) (2 *b + 4) + (b + 7) = 4b, so b =
    1. 6 (x โ€“ 3)(x โ€“ 6) = x^2 โ€“ (6 + 3)x + 6*3 = x^2 - 11x +
    • Therefore: 6 + 3 = b + 1m, so b =
    • Also, 6*3 = (18) 10 = (22)
  • 1.7 64CD 16 = 0110_0100_1100_11 012 = 110_010_011_001 _101 = ( 62315 )
    • Answer: 1111 _ 10102 = FA 43110 = 215 (1); 107 (1); 5 3( 1 ); 26 (1); 1 3(0); 6 (1) 3 ( 0 ) 1(1)
    • Answer: FA = 1111_ 43110 = 26(15); 1(10) (Faster)
    1. 9 (a) 10110.0101 2 = 16 + 4 + 2 + .25 + .0625 = 22.
    • (b) 16.5 16 = 16 + 6 + 5*(.0615) = 22.
    • (c) 26.24 8 = 2 * 8 + 6 + 2/8 + 4/64 = 22.
    • (d) DADA.B 16 = 14 16^3 + 1016^2 + 1 4 *16 + 10 + 11/16 = 60,138.
      • 2710 =
      • .315 x 2 = 0 + .630 a- 1 = Integer Fraction Coefficient
      • .630 x 2 = 1 + .26 a- 2 =
      • .26 x 2 = 0 + .52 a- 3 =
      • .52 x 2 = 1 + .04 a- 4 =
      • .315 10 โ‰… .0101 2 = .25 + .0625 =.
      • 27.315 โ‰… 11011.0101
    • (b) 2/3 โ‰…
      • 6666 _ 6666 _ 67 x 2 = 1 + 3333 _ 3333 _ 34 a- 1 = Integer Fraction Coefficient
      • 3333333334 x 2 = 0 + 6666666668 a- 2 =
      • 6666666668 x 2 = 1 + 3333333336 a- 3 =
      • 3333333336 x 2 = 0 + 6666666672 a- 4 =
      • 66 66666672 x 2 = 1 + 3333333344 a- 5 =
      • 33 33333344 x 2 = 0 + 6666666688 a- 6 =
      • 66 66666688 x 2 = 1 + .3 333333376 a- 7 =
      • 33 33333376 x 2 = 0 + .6666666752 a- 8 =
      • 666666666710 โ‰… 101010102 = .5 + .125 + .0313 + ..0078 = .6641
  • 1.14 (a) 0001 _ 0000 (b) 0000_0000 (c) 1101_ .101010102 = .1010_1010 2 = .AA 16 = 10/16 + 10/256 = .6641 10 (Same as (b)). - 1s comp: 1110 _1111 1s comp: 1111 1111 1s comp: 0010 - 2s comp: 1111 0000 2s comp: 0000_0000 2s comp: 0010
    • (d) 1010_1010 (e) 1000_0101 (f) 1111_
      • 1s comp: 0101_0101 1s comp: 0111_1010 1s comp: 0000_
      • 2s comp: 0101_0110 2s comp: 0111_1011 2s comp: 0000_
  • 1.15 (a) 25,478,036 (b) 63,325, ` - 9s comp: 74,521,963 9s comp: 36,674, - 10s comp: 74,521,964 10s comp: 36,674,
    • (c) 25,000,000 (d)
      • 9s comp: 74,999,999 9s comp:
      • 10s comp: 75,000,000 10s comp:
  • 1.16 C3DF C3DF: 1100_0011_1101_ - 15s comp: 3 C20 1s comp: 0011_1100_0010_ - 16s comp: 3 C21 2s comp: 0011_1100_0010_0001 = 3 C - 4637 โ€“ 2,579 = 2,579 + 97,421 = 1.17 (a) 2,579 โ†’ 0 2,579 โ†’ 9 7,420 (9s comp) โ†’ 9 7,421 (10s comp) - Magnitude: 125 โ€“ 1800 = 00125 + 98200 = 98325 (negative) - Result: 125 โ€“ 1800 =

Digital Design With An Introduction to the Verilog HDL โ€“ Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, (c) 4,361 โ†’ 04361 โ†’ 95638 (9s comp) โ†’ 95639 (10s comp) 2043 โ€“ 4361 = 02043 + 9 5639 = 97682 (Negative) Magnitude: 2318 Result: 2043 โ€“ 6152 = - 2318 (d) 745 โ†’ 00745 โ†’ 99254 (9s comp) โ†’ 99255 (10s comp) 1631 - 745 = 01631 + 99255 = 0886 (Positive) Result: 1631 โ€“ 745 = 886 1.18 Note: Consider sign extension with 2s complement arithmetic. (a) 0_ 10010 ( b) 0_ 1s comp: 1_ 01101 1s comp: 1 011001 with sign extension 2 s comp: 1 01110 2s comp: 1_ 0_ 10011 0_ 100010 Diff: 0_ 00001 (Positive) 1 111100 sign bit indicates that the result is negative Check:19-18 = +1 0_000011 1 s complement 0_000100 2s complement 000100 magnitude Result: - 4 Check: 34 - 38 = - 4 (c) 0_110101 ( d ) 0_0 10101 1s comp: 1_001010 1s comp: 1 101010 with sign extension 2s comp: 1 _ 001011 2s comp: 1_ 101011 0_ 001001 0_ Diff: 1 _ 010100 (negative) 0 _ 010011 sign bit indicates that the result is positive 0_ 101011 ( 1 s comp) Result: 19 10 0_10110 0 (2s complement) Check: 40 โ€“ 21 = (^1910) 101100 (magnitude)

  • 4410 (result) 1. 19 +9286 โ†’ 009286; +801 โ†’ 000801; - 9286 โ†’ 990714; - 801 โ†’ 999199 (a) (+9286) + (801) = 009286 + 000801 = 010087 (b) (+9286) + (-801) = 009286 + 999199 = 008485 (c) (-9286) + (+801) = 990714 + 000801 = 991515 (d) (-9286) + (-801) = 990714 + 999199 = 989913 1.20 +49 โ†’ 0 110001 (Needs leading zero extension to indicate + value); +29 โ†’ 0_011101 (Leading 0 indicates + value)
  • 49 โ†’ 1_ 00111 0 + 0_000001โ†’ 1_ 001111
  • 29 โ†’ 1_100011 (sign extension indicates negative value) (a) (+29) + (- 49 ) = 0_011101 + 1_ 001111 = 1_ 101100 (1 indicates negative value.) Magnitude = 0_010011 + 0_000001 = 0_010100 = 20; Result (+29) + (-49) = - 20 (b) (-29) + (+49) = 1_ 100011 + 0_110001 = 0_010100 (0 indicates positive value) (-29) + (+49) = +

Digital Design With An Introduction to the Verilog HDL โ€“ Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, 1.26 6,248 9s Comp: 3, 2421 code: 0011 _ 0111 0101 0001 1s comp c: 1001 _ 1101 _ 1011 _0001 (2421 code alternative #1) 6,248 2421 0110_0010_0100_1110 (2421 code alternative #2) 1s comp c 1001_1101_1011_0001 Match

Digital Design With An Introduction to the Verilog HDL โ€“ Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, 1.27 For a deck with 52 cards, we need 6 bits ( 25 = 32 < 52 < 64 = 2^6 ). Let the msb's select the suit (e.g., diamonds, hearts, clubs, spades are encoded respectively as 00, 01, 10, and 11. The remaining four bits select the "number" of the card. Example: 0001 (ace) through 1011 (9), plus 101 through 1100 (jack, queen, king). This a jack of spades might be coded as 11_1010. (Note: only 52 out of 64 patterns are used.) 1.28 G (dot) (space) B o o l e 1 1000111_11101111_01101000_01101110_00100000_11000100_11101111_

1. 29 Steve Jobs 1.30 73 F4 E5 76 E5 4A EF 62 73 73: 0 _ 111 _0011 s F4: 1_111_0100 t E5: 1_110_0101 e 76: 0_111_0110 v E5: 1_110_0101 e 4A: 0_100_1010 j EF: 1_110_1111 o 62: 0_110_0010 b 73: 0_111_0011 s 1. 31 62 + 32 = 94 printing characters 1. 32 bit 6 from the right 1. 33 (a) 897 (b) 564 (c) 871 (d) 2, 1.3 4 ASCII for decimal digits with even parity: (0): 00110000 (1): 10110001 (2): 10110010 (3): 00110011 (4): 10110100 (5): 00110101 (6): 00110110 (7): 10110111 (8): 10111000 (9): 00111001 1.35 (a) a b c f g a b c f g 1. a b f g a b f g

Digital Design With An Introduction to the Verilog HDL โ€“ Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, (b) x'yz + xz = (x'y + x)z = z(x + x')(x + y) = z(x + y) (c) (x + y)'(x' + y') = x'y'(x' + y') = x'y' (d) xy + x(wz + wz') = x(y +wz + wz') = x(w + y) (e) (BC' + A'D)(AB' + CD') = BC'AB' + BC'CD' + A'DAB' + A'DCD' = 0 (f) (a' + c')(a + b' + c') = a'a + a'b' + a'c' + c'a + c'b' + c'c' = a'b' + a'c' + ac' + b'c' = c' + b'(a' + c') = c' + b'c' + a'b' = c' + a'b'

2. 4 (a) A'C' + ABC + AC' = C' + ABC = (C + C')(C' + AB) = AB + C' (b) (x'y' + z)' + z + xy + wz = (x'y')'z' + z + xy + wz =[ (x + y)z' + z] + xy + wz = = (z + z')(z + x + y) + xy + wz = z + wz + x + xy + y = z(1 + w) + x(1 + y) + y = x + y + z (c) A'B(D' + C'D) + B(A + A'CD) = B(A'D' + A'C'D + A + A'CD) = B(A'D' + A + A'D(C + C') = B(A + A'(D' + D)) = B(A + A') = B (d) (A' + C)(A' + C')(A + B + C'D) = (A' + CC')(A + B + C'D) = A'(A + B + C'D) = AA' + A'B + A'C'D = A'(B + C'D) (e) ABC'D + A'BD + ABCD = AB(C + C')D + A'BD = ABD + A'BD = BD 2.5 (a) x y F Fsimplified (b) x y F Fsimplified (c)

Digital Design With An Introduction to the Verilog HDL โ€“ Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, x y z Fsimplified F (d) B F Fsimplified A 0 (e) x y z Fsimplified F (f)

Digital Design With An Introduction to the Verilog HDL โ€“ Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, (d) w x y z Fsimplified F (e) A B C D Fsimplified = 0 F (f) w x y z Fsimplified F 2.7 (a) A B C D Fsimplified F

Digital Design With An Introduction to the Verilog HDL โ€“ Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, (b) w x y z Fsimplified F (c) A B C D Fsimplified F (d) A B C D Fsimplified F

Digital Design With An Introduction to the Verilog HDL โ€“ Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, (a) A AND B = 1010_ (b ) A OR B = 1011_1 101 (c) A XOR B = 0001_ (d) NOT A = 0100_ (e) NOT B = 0101_ 2.13 (a) u x y Y = [(u + x')(y' + z)] z (u + x') (y' + z) (b) u x y Y = (u xor y)' + x (u xor y)' x (c) u x y Y = (u'+ x')(y + z') z (u'+ x') (y + z') (d) u x y Y = u(x xor z) + y' z u(x xor z) y' (e) u x y Y = u + yz +uxy z (^) u yz uxy (f)

Digital Design With An Introduction to the Verilog HDL โ€“ Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, u x y Y = u + x + x'(u + y') x'(u + y') (u + y')

2. 14 (a) x y F =xy + x'y' + y'z z (b) x y F = xy + x'y' + y'z = ( x' + y' )' + ( x + y )' + ( y + z' )' z (c) x y F = xy + x'y' + y'z = [(xy)' (x'y')' (y'z)']' z (d) x y F = xy + x'y' + y'z = [(xy)' (x'y')' (y'z)']' z

Digital Design With An Introduction to the Verilog HDL โ€“ Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,

2. 17 (a) F = (b + cd)(c + bd) bc + bd + cd + bcd = ฮฃ (3, 5, 6, 7, 11, 14, 15) F' = ฮฃ (0, 1, 2, 4, 8, 9, 10, 12, 13) F = ฮ  (0, 1, 2, 4, 8, 9, 10, 12, 13) a b c d F 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 1 1 1 0 0 0 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 (b) (cd + b'c + bd')(b + d) = bcd + bd' + cd + b'cd = cd + bd' = ฮฃ (3, 4, 7, 11, 12,14, 15) = ฮ  (0, 1, 2, 5, 6, 8, 9, 10, 13) a b c d F 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 (c) (c' + d)(b + c') = bc' + c' + bd + c'd = (c' + bd) = ฮฃ (0, 1, 4, 5, 7, 8, 12, 13, 15) F = ฮ  (2, 3, 6, 9, 10, 11, 14)

Digital Design With An Introduction to the Verilog HDL โ€“ Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, (d) bd' + acd' + ab'c + a'c' = ฮฃ (0, 1, 4, 5, 10, 11, 14) F' = ฮฃ (2, 3, 6, 7, 8, 9, 12, 13, 15) F = ฮ  (02, 3, 6, 7, 8, 12, 13, 15) a b c d F 0 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 1 1 0 0 1 0 0 1 0 1 0 1 1 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 0