Embedded Systems: Memory Architectures and Microprocessors, Slides of Computer Science

Download Embedded Systems: Memory Architectures and Microprocessors and more Slides Computer Science in PDF only on Docsity!

3-Software Design Basics in

Embedded Systems

Two Memory Architectures

• Princeton

– Fewer memory

wires

• Harvard

– Simultaneous

program and

data memory

access

Processor

Program

memory

Data memory

Processor

Memory

(program and data)

Harvard Princeton

Programmer’s View

• Programmer doesn’t need detailed understanding of architecture

• Instead, needs to know what instructions can be executed

• Two levels of instructions:

• Assembly level
• Structured languages (C, C++, Java, etc.)

• Most development today done using structured languages

• But, some assembly level programming may still be necessary
• Drivers: portion of program that communicates with and/or controls (drives) another

device

• Often have detailed timing considerations, extensive bit manipulation
• Assembly level may be best for these

Assembly-Level Instructions

• Instruction Set

– Defines the legal set of instructions for that

processor

• Data transfer: memory/register, register/register, I/O,

etc.

• Arithmetic/logical: move register through ALU and back^5

opcode operand1 operand

opcode operand1 operand

opcode operand1 operand

opcode operand1 operand

Instruction 1

Instruction 2

Instruction 3

Instruction 4

Addressing Modes

Data

Immediate

Register-direct

Register

indirect

Direct

Indirect

Data

Operand field

Register address

Register address

Memory address

Memory address

Memory address Data

Data

Memory address

Data

Addressing

mode

Register-file

contents

Memory

contents

Sample Programs

• Try some others

• Handshake: Wait until the value of M[254] is not 0, set M[255] to 1, wait until M[254] is

0, set M[255] to 0 (assume those locations are ports).

• (Harder) Count the occurrences of zero in an array stored in memory locations 100

through 199.

int total = 0;

for (int i=10; i!=0; i--)

total += i;

// next instructions...

C program

MOV R0, #0; // total = 0

MOV R1, #10; // i = 10

JZ R1, Next; // Done if i=

ADD R0, R1; // total += i

MOV R2, #1; // constant 1

JZ R3, Loop; // Jump always

Loop:

Next: // next instructions...

SUB R1, R2; // i--

Equivalent assembly program

MOV R3, #0; // constant 0

Microprocessor Selection

• If you are using a particular microprocessor,

now is a good time to review its architecture

• ASIPs :Application Specific Instruction Set

Processors

Application-Specific Instruction-Set

Processors (ASIPs)

• General-purpose processors

– Sometimes too general to be effective in

demanding application

• e.g., video processing – requires huge video buffers and

operations on large arrays of data, inefficient on a GPP

– But single-purpose processor has high NRE, not

programmable

• ASIPs – targeted to a particular domain

– Contain architectural features specific to that

domain

• e.g., embedded control, digital signal processing, video

processing, network processing, telecommunications, 11

Another Common ASIP: Digital

Signal Processors (DSP)

• For signal processing applications

– Large amounts of digitized data, often streaming

– Data transformations must be applied fast

– e.g., cell-phone voice filter, digital TV, music

synthesizer

• DSP features

– Several instruction execution units

– Multiple-accumulate single-cycle instruction,

other instrs.

– Efficient vector operations – e.g., add two arrays 13

Trend: Even More Customized

ASIPs

• In the past, microprocessors were acquired as chips

• Today, we increasingly acquire a processor as Intellectual Property (IP)

• e.g., synthesizable VHDL model

• Opportunity to add a custom datapath hardware and a few custom instructions, or

delete a few instructions

• Can have significant performance, power and size impacts
• Problem: need compiler/debugger for customized ASIP
  • Remember, most development uses structured languages
  • One solution: automatic compiler/debugger generation
    • e.g., www.tensillica.com
  • Another solution: retargettable compilers
    • e.g., www.improvsys.com (customized VLIW architectures)

General Purpose Processors

Processor Clock speed Periph. Bus Width MIPS Power Trans. Price

General Purpose Processors

Intel PIII 1GHz 2x16 K

L1, 256K

L2, MMX

32 ~900 97W ~7M $

IBM

PowerPC

750X

550 MHz 2x32 K

L1, 256K

L

32/64 ~1300 5W ~7M $

MIPS

R

250 MHz 2x32 K

2 way set assoc.

32/64 NA NA 3.6M NA

StrongARM

SA-

233 MHz None 32 268 1W 2.1M NA

Microcontroller

Intel

12 MHz 4K ROM, 128 RAM,

32 I/O, Timer, UART

8 ~1 ~0.2W ~10K $

Motorola

68HC

3 MHz 4K ROM, 192 RAM,

32 I/O, Timer, WDT,

SPI

8 ~.5 ~0.1W ~10K $

Digital Signal Processors

TI C5416 160 MHz 128K, SRAM, 3 T

Ports, DMA, 13

ADC, 9 DAC

16/32 ~600 NA NA $

Lucent

DSP32C

80 MHz 16K Inst., 2K Data,

Serial Ports, DMA

32 40 NA NA $

Sources: Intel, Motorola, MIPS, ARM, TI, and IBM Website/Datasheet; Embedded Systems Programming, Nov. 1998

Designing a General Purpose

Processor

• Not something an embedded system

designer normally would do

• But instructive to see how simply we

can build one top down

• Remember that real processors aren’t

usually built this way

• Much more optimized, much

more bottom-up design

Declarations:

bit PC[16], IR[16];

bit M[64k][16], RF[16][16];

Aliases: op IR[15..12] rn IR[11..8] rm IR[7..4]

dir IR[7..0] imm IR[7..0] rel IR[7..0]

Reset

Fetch

Decode

IR=M[PC];

PC=PC+

Mov1 RF[rn] = M[dir]

Mov

Mov

Mov

Add

Sub

Jz

op = 0000

M[dir] = RF[rn]

M[rn] = RF[rm]

RF[rn]= imm

RF[rn] =RF[rn]+RF[rm]

RF[rn] = RF[rn]-RF[rm]

PC=(RF[rn]=0) ?rel :PC

to Fetch

to Fetch

to Fetch

to Fetch

to Fetch

to Fetch

to Fetch

PC=0;

from states below

FSMD

A Simple Microprocessor

FSM operations that replace the FSMD

operations after a datapath is created

RFwa=rn; RFwe=1; RFs=01; Ms=01; Mre=1;

RFr1a=rn; RFr1e=1; Ms=01; Mwe=1;

RFr1a=rn; RFr1e=1; Ms=10; Mwe=1;

RFwa=rn; RFwe=1; RFs=10;

RFwa=rn; RFwe=1; RFs=00; RFr1a=rn; RFr1e=1; RFr2a=rm; RFr2e=1; ALUs= RFwa=rn; RFwe=1; RFs=00; RFr1a=rn; RFr1e=1; RFr2a=rm; RFr2e=1; ALUs= PCld= ALUz; RFrla=rn; RFrle=1;

MS=10;

Irld=1; Mre=1; PCinc=1;

Reset^ PCclr=1;

Fetch

Decode

IR=M[PC];

PC=PC+

Mov1 RF[rn] = M[dir]

Mov

Mov

Mov

Add

Sub

Jz

op = 0000

M[dir] = RF[rn]

M[rn] = RF[rm]

RF[rn]= imm

RF[rn] =RF[rn]+RF[rm]

RF[rn] = RF[rn]-RF[rm]

PC=(RF[rn]=0) ?rel :PC

to Fetch

to Fetch

to Fetch

to Fetch

to Fetch

to Fetch

to Fetch

PC=0;

from states below

FSMD

Datapath

PC IR

Controller (Next-state and control logic; state register)

Memory

RF (16)

RFwa

RFwe

RFr1a

RFr1e

RFr2a

RFr2e

RFr1 RFr

RFw

ALU

ALUs

2x1 mux

ALUz

RFs

PCld PCinc

PCclr

Ms 3x1 mux MreMwe

To all input contro l signals

From all output control signals

Control unit

Irld

A D

You just built a simple microprocessor!

Example: parallel port driver

• Using assembly language programming we can configure a PC parallel port to

perform digital I/O

• write and read to three special registers to accomplish this table provides list of parallel

port connector pins and corresponding register location

• Example : parallel port monitors the input switch and turns the LED on/off accordingly

PC Parallel port

Pin 13

Pin 2

Switch

LED

LPT Connection Pin I/O Direction Register Address

1 Output 0 th^ bit of register

2-9 Output 0 th^ bit of register

14,16,17 Output 1,2,3th^ bit of register

10,11,12,13,15 Input 6,7,5,4,3th^ bit of register