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Shared Memory Multiprocessor-Parallel Processing-Assignments, Exercises of Parallel Computing and Programming

This assignment was assigned by Prof. Rasul Rangarajan at Deenbandhu Chhotu Ram University of Science and Technology for Parallel Processing course. It includes: Routing, Algorithm, Cache, Block, Wrap, Subroutine, SMP, MESI, State, Memory

Typology: Exercises

2011/2012

Uploaded on 07/23/2012

parama
parama 🇮🇳

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Question # 1 (Marks 30)
a) Give the routing algorithm for a ring
b) Use part (a) as a subroutine & hence give the routing algorithm for k-
d mesh (with wrap around)
c) For a 3-D (no wrap) mesh (row x column x depth )= p x q r & p>q>r;
Find the link cost, diameter & bisection width of this mesh
Question # 2 (Marks 30)
A 3 processor (P1, P2, P3) SMP system has implemented MESI cache
coherent protocol. Give operation, state and cache block contents in each
processor cache memory and main memory. Use dirty bit and least recently
used block replacement policy for main memory write back. Main memory
has 4 cache blocks and processor cache memory has two cache blocks.
Initial contents of the main memory
Processor P2 reads Q.
Processor P3 reads R.
Processor P1 reads L.
Processor P3 reads U.
Processor P2 writes 9 in Q.
Processor P1 writes 10 in L.
Processor P3 writes 7 in U.
Processor P3 writes 8 in R.
Processor P3 reads P.
S
4
L
U
6
5
P
1
R
Q
3
2
Cache block 1
Cache block 2
Cache block 3
Cache block 4
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Question # 1 (Marks 30) a) Give the routing algorithm for a ring b) Use part (a) as a subroutine & hence give the routing algorithm for k- d mesh (with wrap around) c) For a 3-D (no wrap) mesh (row x column x depth )= p x q r & p>q>r; Find the link cost, diameter & bisection width of this mesh

Question # 2 (Marks 30) A 3 processor (P1, P2, P3) SMP system has implemented MESI cache coherent protocol. Give operation, state and cache block contents in each processor cache memory and main memory. Use dirty bit and least recently used block replacement policy for main memory write back. Main memory has 4 cache blocks and processor cache memory has two cache blocks. Initial contents of the main memory

Processor P2 reads Q. Processor P3 reads R. Processor P1 reads L. Processor P3 reads U. Processor P2 writes 9 in Q. Processor P1 writes 10 in L. Processor P3 writes 7 in U. Processor P3 writes 8 in R. Processor P3 reads P.

S 4

L

U

P 1

R

Q

Cache block 1

Cache block 2

Cache block 3

Cache block 4

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Question # 3 (Marks 30) A shared memory multiprocessor with 256 processor uses directory based cache coherence and has 4 GB of memory with cache link/block size of 128 memories. Assume two status bits for each cache block/line. Now assuming at the most 5 simultaneous copies of cache blocks are allowed. Use an efficient scheme to reduce the directory size and hence, compute the size of the directory.

Question # 4 (Marks 30) a) Draw 5 x 4 mesh and assign Id’s to its nodes starting with (0,0) for the top-left node. Also draw a 12 node ring with node id from A,B…..L.

Embed the mesh and ring both into a suitable sized hypercube. Show the mesh Id’s and links in the hypercube using different color.

b) Embed above hypercube into a 8 x 4 mesh.

c) Give the dilation and congestion for the mappings in part a) and b).

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