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A set of lecture notes from CS 150 - Fall 2005 covering the topics of sequential logic, latches, flip-flops, and counters. The notes include diagrams, truth tables, state diagrams, and explanations of the behavior of R-S latches, master-slave flip-flops, and edge-triggered D flip-flops. The document also discusses the differences between latches and flip-flops and the advantages of edge-triggered flip-flops.
Typology: Lecture notes
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CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 1
CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 2
comparator
value
equal
multiplexer
reset
open/closed
new equal
mux
control
clock
comb. logic
state
State is memory
State is an "output" and an "input" to combinational logic
Combination storage elements are also memory
CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 3
Xn
switching
network
Zn
CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 4
"remember"
"load"
"data"
"stored value"
"stored value"
Similar to inverter pair, with capability to force output to 0
(reset=1) or 1 (set=1)
Similar to inverter pair, with capability to force output to 0
(reset=0) or 1 (set=0)
Reset Hold Set Reset Set Race
CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 7
0 0 hold
1 1 unstable
CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 8
States: possible values
Transitions: changes
based on inputs
CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 9
CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 10
Q(t+Δ)
Q(t)
S R Q(t) Q(t+Δ)
hold
reset
set
not allowed characteristic equation
Q(t+Δ) = S + R’ Q(t)
0 0
1 0
X 1
Q(t) X 1
enable'
Set
Reset
enable'
period
duty cycle (in this case, 50%)
CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 19
Clk=
when clock goes high-to-low
data is latched
when clock is low
data is held
new D
Clk=
new D ≠ old D
CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 20
Clk=
CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 21
Clk=
CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 22
Clk=
positive edge-triggered FF
negative edge-triggered FF
Qpos
Qpos'
Qneg
Qneg'
CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 25
Guarantee proper operation of system when strictly followed
Focus on systems with edge-triggered flip-flops
Found in programmable logic devices
Many custom integrated circuits focus on level-sensitive latches
(1) Correct inputs, with respect to time, are provided to the flip-flops
(2) No flip-flop changes state more than once per clocking event
CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 26
there is a timing "window"
around the clocking event
during which the input must
remain stable and unchanged
in order to be recognized
clock
data
stable changing
input
clock
su
h
clock
data
CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 27
behavior is the same unless input changes
while the clock is high
positive
edge-triggered
flip-flop
transparent
(level-sensitive)
latch
Qedge
Qlatch
CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 28
Type When inputs are sampled When output is valid
unclocked always propagation delay from input change
latch
level-sensitive clock high propagation delay from input change
latch (Tsu/Th around falling or clock edge (whichever is later)
edge of clock)
master-slave clock high propagation delay from falling edge
flip-flop (Tsu/Th around falling of clock
edge of clock)
negative clock hi-to-lo transition propagation delay from falling edge
edge-triggered (Tsu/Th around falling of clock
flip-flop edge of clock)
all measurements are made from the clocking event that is,
the rising edge of the clock
Th
5ns
Tw 25ns
Tplh
25ns
13ns
Tphl
40ns
25ns
Tsu
20ns
Tsu
20ns
Th
5ns
IN
Q
Q
CLK
100
CLK
CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 37
CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 38
CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 39
clear sets the register contents
and output to 0
s1 and s0 determine the shift function
s0 s1 function
0 0 hold state
0 1 shift right
1 0 shift left
1 1 load new input
left_in
left_out
right_out
clear
right_in
output
input
s
s
clock
CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 40
Nth cell
s0 and s
control mux
(left)
(right)
Input[N]
to N-1th
cell
to N+1th
cell
clear s0 s1 new value
1 – – 0
0 0 0 output
0 0 1 output value of FF to left (shift right)
0 1 0 output value of FF to right (shift left)
0 1 1 input
module univ_shift (out, lo, ro, in, li, ri, s, clr, clk);
output [3:0] out;
output lo, ro;
input [3:0] in;
input [1:0] s;
input li, ri, clr, clk;
reg [3:0] out;
assign lo = out[3];
assign ro = out[0];
always @(posedge clk or clr)
begin
if (clr) out <= 0;
else
case (s)
3: out <= in;
2: out <= {out[2:0], ri};
1: out <= {li, out[3:1]};
0: out <= out;
endcase
end
endmodule
parallel inputs
parallel outputs
serial transmission
CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 43
CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 44
CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 45
CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 46
EN
D
C
B
A
LOAD
CLK
CLR
RCO
QD
QC
QB
QA
(1) Low order 4-bits = 1111
(2) RCO goes high
(3) High order 4-bits
are incremented
high when counter is in its highest state 1111
implemented using an AND gate