Docsity
Docsity

Prepare for your exams
Prepare for your exams

Study with the several resources on Docsity


Earn points to download
Earn points to download

Earn points by helping other students or get them with a premium plan


Guidelines and tips
Guidelines and tips

Sequential Logic: Lecture Notes on Latches, Flip-Flops, and Counters from CS 150 Fall 2005, Lecture notes of Logic

A set of lecture notes from CS 150 - Fall 2005 covering the topics of sequential logic, latches, flip-flops, and counters. The notes include diagrams, truth tables, state diagrams, and explanations of the behavior of R-S latches, master-slave flip-flops, and edge-triggered D flip-flops. The document also discusses the differences between latches and flip-flops and the advantages of edge-triggered flip-flops.

Typology: Lecture notes

2021/2022

Uploaded on 09/27/2022

gerrard_11
gerrard_11 🇬🇧

4.3

(6)

234 documents

1 / 9

Toggle sidebar

This page cannot be seen from the preview

Don't miss anything!

bg1
CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 1
Sequential Logic
Sequential Circuits
Simple circuits with feedback
Latches
Edge-triggered flip-flops
Timing Methodologies
Cascading flip-flops for proper operation
Clock skew
Basic Registers
Shift registers
Counters
CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 2
C1 C2 C3
comparator
value
equal
multiplexer
reset
open/closed
new equal
mux
control
clock
comb. logic
state
Sequential Circuits
Circuits with Feedback
Outputs = f(inputs, past inputs, past outputs)
Basis for building "memory" into logic circuits
Door combination lock is an example of a sequential circuit
State is memory
State is an "output" and an "input" to combinational logic
Combination storage elements are also memory
CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 3
X1
X2
Xn
switching
network
Z1
Z2
Zn
Circuits with Feedback
How to control feedback?
What stops values from cycling around endlessly
CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 4
"remember"
"load"
"data" "stored value"
"0"
"1"
"stored value"
Simplest Circuits with Feedback
Two inverters form a static memory cell
Will hold value as long as it has power applied
How to get a new value into the memory cell?
Selectively break feedback path
Load new value into cell
CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 5
R
S
Q
Q'
R
S
Q
R'
S'
QQ
Q'
S'
R'
Memory with Cross-coupled Gates
Cross-coupled NOR gates
Similar to inverter pair, with capability to force output to 0
(reset=1) or 1 (set=1)
Cross-coupled NAND gates
Similar to inverter pair, with capability to force output to 0
(reset=0) or 1 (set=0)
CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 6
Reset Hold Set SetReset Race
R
S
Q
\Q
100
Timing Behavior
R
S
Q
Q'
pf3
pf4
pf5
pf8
pf9

Partial preview of the text

Download Sequential Logic: Lecture Notes on Latches, Flip-Flops, and Counters from CS 150 Fall 2005 and more Lecture notes Logic in PDF only on Docsity!

CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 1

Sequential Logic

 Sequential Circuits

 Simple circuits with feedback

 Latches

 Edge-triggered flip-flops

 Timing Methodologies

 Cascading flip-flops for proper operation

 Clock skew

 Basic Registers

 Shift registers

 Counters

CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 2

C1 C2 C

comparator

value

equal

multiplexer

reset

open/closed

new equal

mux

control

clock

comb. logic

state

Sequential Circuits

 Circuits with Feedback

 Outputs = f(inputs, past inputs, past outputs)

 Basis for building "memory" into logic circuits

 Door combination lock is an example of a sequential circuit

 State is memory

 State is an "output" and an "input" to combinational logic

 Combination storage elements are also memory

CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 3

X
X

Xn

switching

network

Z
Z

Zn

Circuits with Feedback

 How to control feedback?

 What stops values from cycling around endlessly

CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 4

"remember"

"load"

"data"

"stored value"

"stored value"

Simplest Circuits with Feedback

 Two inverters form a static memory cell

 Will hold value as long as it has power applied

 How to get a new value into the memory cell?

 Selectively break feedback path

 Load new value into cell

R
S
Q
Q'
R
S
Q
R'
S'
Q
Q
Q'
S'
R'

Memory with Cross-coupled Gates

 Cross-coupled NOR gates

 Similar to inverter pair, with capability to force output to 0

(reset=1) or 1 (set=1)

 Cross-coupled NAND gates

 Similar to inverter pair, with capability to force output to 0

(reset=0) or 1 (set=0)

Reset Hold Set Reset Set Race

R
S
Q
\Q

Timing Behavior

R
S
Q
Q'

CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 7

S R Q

0 0 hold

1 1 unstable

State Behavior of R-S latch

 Truth table of R-S latch behavior

Q Q'
Q Q'
Q Q'
Q Q'

CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 8

Theoretical R-S Latch Behavior

 State Diagram

 States: possible values

 Transitions: changes

based on inputs

Q Q'
Q Q'
Q Q'
Q Q'
SR=
SR=
SR=
SR=
SR=
SR=
SR=
SR=
SR=
SR=11 SR=
SR=
SR=
SR=01 SR=
SR=

possible oscillation

between states 00 and 11

CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 9

Observed R-S Latch Behavior

 Very difficult to observe R-S latch in the 1-1 state

 One of R or S usually changes first

 Ambiguously returns to state 0-1 or 1-

 A so-called "race condition"

 Or non-deterministic transition

SR=
SR=
Q Q'
Q Q'
Q Q'
SR=
SR=
SR=
SR=
SR=
SR=
SR=11 SR=
SR=01 SR=
SR=

CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 10

R
S
Q
Q'

Q(t+Δ)

R
S

Q(t)

S R Q(t) Q(t+Δ)

1 1 0 X
1 1 1 X

hold

reset

set

not allowed characteristic equation

Q(t+Δ) = S + R’ Q(t)

R-S Latch Analysis

 Break feedback path

0 0

1 0

X 1

Q(t) X 1

R
S

enable'

S'
Q'
Q
R'
R
S

Gated R-S Latch

 Control when R and S

inputs matter

 Otherwise, the

slightest glitch on R

or S while enable is

low could cause

change in value stored

Set

Reset

S'
R'

enable'

Q
Q'

period

duty cycle (in this case, 50%)

Clocks

 Used to keep time

 Wait long enough for inputs (R' and S') to settle

 Then allow to have effect on value stored

 Clocks are regular periodic signals

 Period (time between ticks)

 Duty-cycle (time clock is high between ticks - expressed as %

of period)

CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 19

Q
D

Clk=

R
S
D
D’
D’
D’
D

when clock goes high-to-low

data is latched

when clock is low

data is held

Edge-Triggered Flip-Flops (cont’d)

 Step-by-step analysis

Q

new D

Clk=

R
S
D
D’
D’
D’
D

new D ≠ old D

CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 20

Q
D

Clk=

R
S
D
D’
D’
D’
D

Edge-Triggered Flip-Flops (cont’d)

 D = 0, Clk High

Hold state

Act as inverters

CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 21

Q
D

Clk=

R
S
D
D’
D’
D’
D

Edge-Triggered Flip-Flops (cont’d)

 D = 1, Clk High

CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 22

Q
D

Clk=

R
S
D
D’
D’
D’
D

Edge-Triggered Flip-Flops (cont’d)

 D = 1, Clk LOW

Act as inverters

positive edge-triggered FF

negative edge-triggered FF

D
CLK

Qpos

Qpos'

Qneg

Qneg'

Edge-Triggered Flip-Flops (cont’d)

 Positive edge-triggered

 Inputs sampled on rising edge; outputs change after rising edge

 Negative edge-triggered flip-flops

 Inputs sampled on falling edge; outputs change after falling edge

Negative Edge Trigger FF in Verilog

module d_ff (q, q_bar, data, clk);

input data, clk;

output q, q_bar;

reg q;

assign q_bar = ~q;

always @(negedge clk)

begin

q <= data;

end

endmodule

CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 25

Timing Methodologies

 Rules for interconnecting components and clocks

 Guarantee proper operation of system when strictly followed

 Approach depends on building blocks used for memory elements

 Focus on systems with edge-triggered flip-flops

 Found in programmable logic devices

 Many custom integrated circuits focus on level-sensitive latches

 Basic rules for correct timing:

 (1) Correct inputs, with respect to time, are provided to the flip-flops

 (2) No flip-flop changes state more than once per clocking event

CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 26

there is a timing "window"

around the clocking event

during which the input must

remain stable and unchanged

in order to be recognized

clock

data

stable changing

input

clock

T

su

T

h

clock

data

D Q D Q

Timing Methodologies (cont’d)

 Definition of terms

 clock: periodic event, causes state of memory element to

change; can be rising or falling edge, or high or low level

 setup time: minimum time before the clocking event by which

the input must be stable (Tsu)

 hold time: minimum time after the clocking event until which

the input must remain stable (Th)

CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 27

behavior is the same unless input changes

while the clock is high

D Q
CLK

positive

edge-triggered

flip-flop

D Q
G
CLK

transparent

(level-sensitive)

latch

D
CLK

Qedge

Qlatch

Comparison of Latches and Flip-Flops

CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 28

Type When inputs are sampled When output is valid

unclocked always propagation delay from input change

latch

level-sensitive clock high propagation delay from input change

latch (Tsu/Th around falling or clock edge (whichever is later)

edge of clock)

master-slave clock high propagation delay from falling edge

flip-flop (Tsu/Th around falling of clock

edge of clock)

negative clock hi-to-lo transition propagation delay from falling edge

edge-triggered (Tsu/Th around falling of clock

flip-flop edge of clock)

Comparison of Latches and Flip-Flops

(cont’d)

all measurements are made from the clocking event that is,

the rising edge of the clock

Typical Timing Specifications

 Positive edge-triggered D flip-flop

 Setup and hold times

 Minimum clock width

 Propagation delays (low to high, high to low, max and typical)

Th

5ns

Tw 25ns

Tplh

25ns

13ns

Tphl

40ns

25ns

Tsu

20ns

D
CLK
Q

Tsu

20ns

Th

5ns

IN

Q

Q

CLK

100

Cascading Edge-triggered Flip-Flops

 Shift register

 New value goes into first stage

 While previous value of first stage goes into second stage

 Consider setup/hold/propagation delays (prop must be > hold)

CLK

IN
Q0 Q
D Q D Q OUT

CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 37

Shift Register Verilog

module shift_reg (out4, out3, out2, out1, in, clk);

output out4, out3, out2, out1;

input in, clk;

reg out4, out3, out2, out1;

always @(posedge clk)

begin

out4 <= out3;

out3 <= out2;

out2 <= out1;

out1 <= in;

end

endmodule

CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 38

Shift Register Verilog

module shift_reg (out, in, clk);

output [4:1] out;

input in, clk;

reg [4:1] out;

always @(posedge clk)

begin

out <= {out[3:1], in};

end

endmodule

CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 39

clear sets the register contents

and output to 0

s1 and s0 determine the shift function

s0 s1 function

0 0 hold state

0 1 shift right

1 0 shift left

1 1 load new input

left_in

left_out

right_out

clear

right_in

output

input

s

s

clock

Universal Shift Register

 Holds 4 values

 Serial or parallel inputs

 Serial or parallel outputs

 Permits shift left or right

 Shift in new values from left or right

CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 40

Nth cell

s0 and s

control mux

D
Q
CLK
CLEAR
Q[N-1]

(left)

Q[N+1]

(right)

Input[N]

to N-1th

cell

to N+1th

cell

clear s0 s1 new value

1 – – 0

0 0 0 output

0 0 1 output value of FF to left (shift right)

0 1 0 output value of FF to right (shift left)

0 1 1 input

Design of Universal Shift Register

 Consider one of the four flip-flops

 New value at next clock cycle:

Universal Shift Register Verilog

module univ_shift (out, lo, ro, in, li, ri, s, clr, clk);

output [3:0] out;

output lo, ro;

input [3:0] in;

input [1:0] s;

input li, ri, clr, clk;

reg [3:0] out;

assign lo = out[3];

assign ro = out[0];

always @(posedge clk or clr)

begin

if (clr) out <= 0;

else

case (s)

3: out <= in;

2: out <= {out[2:0], ri};

1: out <= {li, out[3:1]};

0: out <= out;

endcase

end

endmodule

parallel inputs

parallel outputs

serial transmission

Shift Register Application

 Parallel-to-serial conversion for serial transmission

CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 43

IN D Q D Q D Q D Q
OUT1 OUT2 OUT3 OUT
CLK
OUT

Pattern Recognizer

 Combinational function of input samples

 In this case, recognizing the pattern 1001 on the single input

signal

CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 44

IN D Q D Q D Q D Q
OUT1 OUT2 OUT3 OUT
CLK
D Q D Q D Q D Q
IN
OUT1 OUT2 OUT3 OUT
CLK

Counters

 Sequences through a fixed set of patterns

 In this case, 1000, 0100, 0010, 0001

 If one of the patterns is its initial state (by loading or

set/reset)

 Mobius (or Johnson) counter

 In this case, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000

CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 45

D Q D Q D Q D Q
OUT1 OUT2 OUT3 OUT
CLK

Binary Counter

 Logic between registers (not just multiplexer)

 XOR decides when bit should be toggled

 Always for low-order bit, only when first bit is true for

second bit, and so on

CS 150 - Fall 2005 – Lec. #5 – Sequential Logic - 46

Binary Counter Verilog

module shift_reg (out4, out3, out2, out1, clk);

output out4, out3, out2, out1;

input in, clk;

reg out4, out3, out2, out1;

always @(posedge clk)

begin

out4 <= (out1 & out2 & out3) ^ out4;

out3 <= (out1 & out2) ^ out3;

out2 <= out1 ^ out2;

out1 <= out1 ^ 1b’1;

end

endmodule

Binary Counter Verilog

module shift_reg (out4, out3, out2, out1, clk);

output [4:1] out;

input in, clk;

reg [4:1] out;

always @(posedge clk)

out <= out + 1;

endmodule

EN

D

C

B

A

LOAD

CLK

CLR

RCO

QD

QC

QB

QA

(1) Low order 4-bits = 1111

(2) RCO goes high

(3) High order 4-bits

are incremented

Four-bit Binary Synchronous Up-Counter

 Standard component with many applications

 Positive edge-triggered FFs w/ sync load and clear inputs

 Parallel load data from D, C, B, A

 Enable inputs: must be asserted to enable counting

 RCO: ripple-carry out used for cascading counters

 high when counter is in its highest state 1111

 implemented using an AND gate