The University of Alabama in Huntsville
ECE Department
CPE 426 01
Midterm Exam
February 26, 2003
1. (25 points) Describe the following logic expression
(A’• B’ • D) + (A • B • C) + (B’ • C’)
with a structural VHDL model using the following package located in library WORK.
Hint: If you don’t need all of the inputs, you can tie one or more of them to ‘0’ or ‘1’.
package LOGIC_PKG is
component AND2_OP
port (A, B : in BIT; Z out BIT);
end component;
component NOR2_OP
port (A, B : in BIT; Z out BIT);
end component;
component OR4_OP
port (A, B, C, D : in BIT; Z out BIT);
end component;
end LOGIC_PKG;
