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The midterm exam for the cpe 426 01 course offered by the ece department at the university of alabama in huntsville. The exam covers various topics related to vhdl modeling and digital systems design, including logic expressions, primary design units in vhdl, edge-triggered flip-flops, priority encoders, and state machines. The exam includes multiple-choice questions, short answer questions, and problems requiring vhdl code development.
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package LOGIC_PKG is component AND2_OP port (A, B : in BIT; Z out BIT); end component; component NOR2_OP port (A, B : in BIT; Z out BIT); end component; component OR4_OP port (A, B, C, D : in BIT; Z out BIT); end component; end LOGIC_PKG;
ENTITY state_machine IS PORT (Clock, Resetn ; IN BIT; r : IN BIT_VECTOR(1 to 3); g : OUT BIT_VECTOR(1 to 3)); END state_machine;
ARCHITECTURE behavior OF state_machine IS TYPE state_type IS (Idle, gnt1, gnt2, gnt3); SIGNAL y : state_type; BEGIN PROCESS (Resetn, Clock) BEGIN IF (Resetn = ‘0’) THEN y <= Idle; ELSIF (Clock’EVENT AND Clock = ‘1’) THEN CASE y IS WHEN Idle => IF (r(1) = ‘1’) THEN y <= gnt1; ELSIF (r(2) = ‘1’) THEN y <= gnt2; ELSIF (r(3) = ‘1’) THEN y <= gnt3; ELSE y <= Idle; END IF ; WHEN gnt1 => IF (r(1) = ‘1’) THEN y <= gnt1; ELSE y <= Idle; END IF ; WHEN gnt2 => IF (r(2) = ‘1’) THEN y <= gnt2; ELSE y <= Idle; END IF ; WHEN gnt3 => IF (r(3) = ‘1’) THEN y <= gnt3; ELSE y <= Idle; END IF ; END CASE ; END IF ; END PROCESS ;
g(1) <= ‘1’ WHEN y = gnt1 ELSE ‘0’; g(2) <= ‘1’ WHEN y = gnt2 ELSE ‘0’; g(3) <= ‘1’ WHEN y = gnt3 ELSE ‘0’;
END behavior;