ECE 491 – Senior Design 1
Laboratory 5 – RS-232 Serial Receiver
September 28, 2006
Introduction
In this lab you will design and implement a serial receiver. It is more complex that the serial
transmitter because it requires that you synchronize with an incoming signal and sample
successive bits. Your design will probably consist of a shift register, one or more counters
(used to generate delays), and a control unit that ties it all together.
Lab Preparation and Design
We will design the serial receiver assuming a clock rate that is 16 times the baud rate. The
receiver circuit must implement the following steps:
1. Wait for the falling edge of the START bit.
2. Delay to the center of the START bit and sample the current data value. If the data
value is not still asserted low, ignore the START bit and return to step 1.
3. Delay to the center of the next data bit. Sample the value of the data value and
shift it into a shift register.
4. Repeat step 3 seven more times.
5. Delay to the center of the stop bit and sample. If the value is not correct, indicate a
framing error condition.
6. Indicate that valid data is available in the shift register.
7. Go back to step 1.
Your asynchronous serial receiver should have the following inputs and outputs:
Asynchronous Serial Rcvr.
RXD
DATA
RDY
FERR
CLOCK
8
RXD is the serial data input. DATA is the parallel data output. RDY should be asserted
when a character has been received, and FERR should be asserted when a character has
been received but the value of the stop bit was not correct (FERR and RDY should remain
asserted until a new start bit is detected).
