Resolved Signals - Theory and Design of Computers - Lecture Slides, Slides of Computer Aided Design (CAD)

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Resolved Signals

What are resolved signals and how do

they work.

Resolution??? Isn’t that for solving

conflicts???

Overview – Resolved Signals

• Why resolved signals?

• Steps to creating a resolved signal in VHDL

• Resolution Functions

Busses and Wires

• Busses on the other hand

can be driven by one or

more sources

• In both cases there can be

more than one destination

for the signal

• With busses, only the

device acting as source will

actually drive a value. All

others will have their

output set at high

impedance (Z).

ENB

ENB

ENB

How do you handle Busses in an HDL?

• First must consider the information present on

a wire and on a bus in a digital circuit.

• Information present on a wire:
  • Wire is limited to 2 states using TYPE BIT
  • High or 1 or ‘1’
  • Low or 0 or ‘0’
  • There is a transition period between the two but

High and Low are the only 2 stable states.

In an HDL need Resolution

• With multiple drivers of a signal how do you

resolve the value seen by devices using the

bus?

• RESOLUTION

– How to determine the value when two or more

drivers are driving the same signal

• Must look at all drivers and determine the

appropriate value to use.

Step needed in VHDL

• Declare a type for the multi-value logic system

– type mv4_logic is (‘X’,’Z’,’0’,’1’):

– type mv4_logic_vector is array (natural range <>) of mv4_logic;

• Then declare a resolution function

– function resolved (s:mv4_logic_vector) RETURN mv4_logic;

• And then the resolved signal

– subtype mv4r_logic is resolved mv4_logic;

– type mv4r_logic_vector is array (natural range <>) of mv4r_logic;

• Note that you need to use a subtype declaration to incorporate

the resolution function.

• So there will be both a resolved and unresolved type for the

multi-value system

Type and Subtype Declaration BNF

• It is, however, in the SUBTYPE definition

– subtype_declaration::=

– SUBTYPE identifier IS subtype_indication

– subtype_indication::=[ resolution_function_name ]

– type_mark [constraint]

– type_mark::= type_name | subtype_name

– constraint::= range_constraint | index_constraint

VHDL specification cont.

• Had declaration for a function resolved

– function resolved(s : mv4_logic_vector) RETURN mv4_logic;

• Then the body of the resolution function is given in the package body

where you will find:

– TYPE mv4_logic_table IS array (mv4_logic,mv4_logic) of mv4_logic;

– CONSTANT resolution_table : mv4_logic_table :=(

– -- | X Z 0 1 | |

– ( ‘X’, ‘X’, ‘X’, ‘X’ ), --| X |

– ( ‘X’, ‘Z’, ‘0’, ‘1’ ), --| Z |

– ( ‘X’, ‘0’, ‘0’, ‘X’ ), --| 0 |

– ( ‘X’, ‘1’, ‘X’, ‘1’ )); --| 1 |

• And having the resolution table can write the body of the resolution func.

The big picture

• After posting of a

transaction(s) to the

current value of one or

more of the drivers, a

vector composed of the

current values of the

drivers is sent to the

resolution function for

determination of the

resolved value.

st

Process for

a <= equation ….

st

Driver for a

CV ‘Z’ t

nd

Process for

a <= 2

nd

equation ….

nd

Driver for a

CV ‘0’ t

n

th

Process for

a <= n

th

equation ….

n

th

Driver for a

CV ‘Z’ t

Resolved

Value

Completeness of a MVL package

• Having a MVL type with resolution is only part

of creating a MVL system.

• ALSO need

– Overloaded function for standard operators

– Type conversion functions to convert from other

type to this type and the reverse

• ieee_1164 standard MVL package is a

standard package for a multi-value logic

system and contains all of these.

Use of Resolved signals

• Must use a resolved signal

type for any signals of mode

INOUT

– PORT ( ABUS : INOUT

mv4r_logic; …

• Within an ARCHITECTURE

they are needed whenever

the signal will have more

than one driver

ARCHITECTURE abcd OF wxyz IS

…

SIGNAL a,b,c : mv4r_logic;

…

BEGIN

a <= ‘0’, ‘1’ after 10 ns, ‘0’ after 20 ns;

p1: process

begin

a <= ‘Z’;

wait …

end process;

p2: process

begin

a <= ‘0’;

wait …

end process;

END abcd;

Driver 1 of a

Driver 2 of a

Driver 3 of a

Standard logic 1164

• Package is online in the

course directory

• Opens with comments

on the code

• What is the first part of

declaring an MVL

system in a package?

-- Title : std_logic_1164 multi-value logic system -- Library : This package shall be compiled into a library -- : symbolically named IEEE. -- : -- Developers: IEEE model standards group (par 1164) -- Purpose : This packages defines a standard for designers -- : to use in describing the interconnection data types -- : used in vhdl modeling. -- : -- Limitation: The logic system defined in this package may -- : be insufficient for modeling switched transistors, -- : since such a requirement is out of the scope of this -- : effort. Furthermore, mathematics, primitives, -- : timing standards, etc. are considered orthogonal -- : issues as it relates to this package and are therefore -- : beyond the scope of this effort. -- : -- Note : No declarations or definitions shall be included in, -- : or excluded from this package. The "package declaration" -- : defines the types, subtypes and declarations of -- : std_logic_1164. The std_logic_1164 package body shall be -- : considered the formal definition of the semantics of -- : this package. Tool developers may choose to implement -- : the package body in the most efficient manner available -- : to them. -- :

---

-- modification history :

---

-- version | mod. date:| -- v4.200 | 01/02/92 |

---

Overload operators

• All operators are

overloaded

• Can find the package in

~degroat/ee762_assign

/std_1164.vhd

-- overloaded logical operators

FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; FUNCTION "or" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; -- function "xnor" ( l : std_ulogic; r : std_ulogic ) return ux01; FUNCTION "not" ( l : std_ulogic ) RETURN UX01;

-- vectorized overloaded logical operators

FUNCTION "and" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "and" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;

FUNCTION "nand" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "nand" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;

FUNCTION "or" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "or" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;

FUNCTION "nor" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "nor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;

FUNCTION "xor" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "xor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;

-- Note : The declaration and implementation of the "xnor" function is -- specifically commented until at which time the VHDL language has been -- officially adopted as containing such a function. At such a point, -- the following comments may be removed along with this notice without -- further "official" ballotting of this std_logic_1164 package. It is -- the intent of this effort to provide such a function once it becomes -- available in the VHDL standard.

---

-- function "xnor" ( l, r : std_logic_vector ) return std_logic_vector; -- function "xnor" ( l, r : std_ulogic_vector ) return std_ulogic_vector;

FUNCTION "not" ( l : std_logic_vector ) RETURN std_logic_vector; FUNCTION "not" ( l : std_ulogic_vector ) RETURN std_ulogic_vector;

Type conversion functions and edge

detection

• To convert from built in

logic types of BIT and

BIT_VECTOR

• And there are similar

conversion functions for

the reduced logic

systems

• Also have functions for

rising and falling edge

-- conversion functions

FUNCTION To_bit ( s : std_ulogic; xmap : BIT := '0') RETURN BIT; FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '0') RETURN BIT_VECTOR; FUNCTION To_bitvector ( s : std_ulogic_vector; xmap : BIT := '0') RETURN BIT_VECTOR;

FUNCTION To_StdULogic ( b : BIT ) RETURN std_ulogic; FUNCTION To_StdLogicVector ( b : BIT_VECTOR ) RETURN std_logic_vector; FUNCTION To_StdLogicVector ( s : std_ulogic_vector ) RETURN std_logic_vector; FUNCTION To_StdULogicVector ( b : BIT_VECTOR ) RETURN std_ulogic_vector; FUNCTION To_StdULogicVector ( s : std_logic_vector ) RETURN std_ulogic_vector;

-- edge detection

FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN; FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN;