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This course focuses on quantitative principle of computer design, instruction set architectures, datapath and control, memory hierarchy design, main memory, cache, hard drives, multiprocessor architectures, storage and I/O systems, computer clusters. This lecture includes: Reorder, Buffer, Fields, Instruction, Commits, value, Speculative, Tomasulo, Algorithm, Execute, Operate
Typology: Slides
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Operate on operands (EX)
If both operands ready then execute
If not ready, the watch CDB for result
This checks for RAW hazards
Instructions may take multiple clock
cycles here
Speculative Tomasulo’s Algorithm
Commit can occur when an instruction reaches the head of the ROB and its result is present in the buffer.
Commit update register or store to memory with ROB result and free up ROB slot
If ROB head is an incorrectly predicted branch, then flush ROB
If the branch was correctly predicted, then the branch is finished
Speculative Tomasulo’s Algorithm
Example 1: Code
L.D F6,34(R2)
L.D F2,45(R3)
MUL.D F0,F2,F
SUB.D F8,F6,F
DIV.D F10,F0,F
ADD.D F6,F8,F
Speculative Tomasulo’s Algorithm
Also note that at the time
Further, here
The DIV.D is in execution, but has not completed
solely due to its longer latency than MUL.D.
Comparing the two tables we can see that
In the non-speculation case, the ADD.D and SUB.D
instructions completed out-of-order, i.e., before
the MUL.D completed
The in case of speculative hardware:
To show how speculation can improve performance in a
multiple issue processor. Let us consider an example.
Example
Consider the execution of the following loop, which
searches an array, on two- issue processor, once without speculation and once with speculation.
Loop: LD R2,0(R1) ; R2= array element DADDUI R2,R2,#1 ; increment R SD R2,0(R1) ; store result DADDUI R1,R1,#4 ; increment pointer BNE R2,R3,LOOP ; branch if not last element