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ECE 4175 RPK/RPY
Test 2
Oct 30, 2002
Name _______ Solution_____________________
Test is open book, open notes. You may use a calculator, and the web.
You may not consult another person directly or indirectly. 50 minutes.
1) (20%) True/False
T F A 16F877 using a 10MHz clock executes a “GOTO” instruction in 500 ns. 1/10MHz = 100ns, 100ns * 4 = 400 ns/instruction cycle, (2) cycles => 800ns
T F The maximum clock frequency for the 16F877 is 25MHz. 20MHz
T F Conditional statements in macros (ie, ‘if’) are evaluated at program runtime. They are evaluated at compile time
T F RP0 and RP1 are used for bank selection when using indirect addressing. IRP is used
T F Multiple interrupts can be pending in the 16F877.
2) (40%) A 16F877 is used as the control CPU to control an automated “drill” which drills holes to a precision depth. The CPU takes inputs from an RPG which senses drill rotation, and drives a stepper motor to move the drill bit up and down. An A/D converter is used to monitor the drilling pressure. The 16F877 is clocked a t 8MHz. (500ns/instruction cycle)
The stepper motor steps once for every timer1 interrupt. The program adjusts the period of timer1 to slow down the up/down movement of the drill as the drill nears the bottom of the drilling. The highest rate of timer1 is one interrupt every 400 microseconds.
Timer 2 is periodic, every 50 ms.
Timer 2 starts an A/D conversion, which takes 900 microseconds.
Completion of the A/D routine causes an A/D interrupt.
The RPG generates an interrupt every 10 degrees of rotation (36 interrupts per full rotation).
Timer2_ISR 200 instructions 100 us (once every 50ms) ( 0.2%) A/D_ISR 150 instructions 75 us (once every 50ms) (0.15%) Timer1_ISR 300 instructions 150 us (every 400 us) (37.5%) RPG_ISR 50 instructions 25 us (36 times per rotation) longest critical region 70 instructions 35 us
a) Neglecting the MASTER_ISR overhead, what is the maximum (worst case) latency for the RPG_ISR?
Since we don’t have the MASTER_ISR order, assume worst possible situation: Critical Region + Timer2 + A/D + Timer1 = 35+100+75+150 = 360us since Timer2 and A/D not likely to be both pending, eliminate shorter one Critical Region + Timer2 + Timer1 = 35+100+150 = 285 us
b) What is the maximum RPM for the drill to run without loosing interrupts?
Will loose an interrupt if RPG interrupt is “pending” when a second RPG interrupt occurs, ie, RPG interrupts occur faster than worst case latency for RPG interrupt
Worst case latency = 360 us => 2777 interrupts/second 36 interrupts per turn: 2777/36 = 77 rotations per second = 4620 rotations per minute (rpm)
c) Using the RPM found in part b, and at the highest timer1 rate of one interrupt every 400 microseconds, what percentage of time is spent servicing interrupts? (Hint, start by calculating how many of each kind of interrupts occur in one second).
2777 interrupts per second * 25us = 69.4ms spent servicing RPG every second (6.94%) 6.94% + 37.5% + .15%+.2% = 44.79%
d) Can all 4 interrupts be simultaneously pending?
Since Timer2 starts A/D, is the worst case latency on A/D long enough to push it into the next timer2 interrupt?
Timer2 interrupts occur every 50ms. Sequence of events is
- Timer2 generates a pending interrupt
3) What value will this code store in Reg9?
Reg1 equ H’70’ Reg2 equ H’71’ Reg3 equ H’72’ Reg4 equ H’73’ Reg5 equ H’74’ Reg6 equ H’75’ Reg7 equ H’76’ Reg8 equ H’77’ Reg9 equ H’78’
Movlw Reg1 Puts H’70’ in W register movwf FSR Puts H’70’ from W into FSR Loop movf FSR,w Puts FSR into W addlw H’03’ Adds 3 to W movwf 0 stores W into register address given by FSR incf FSR,f increments FSR movlw H’79’ Puts H’79’ into W subwf FSR,w calculates FSR - W btfss STATUS,Z if FSR – W = 0 (ie, FSR = H’79’), skip goto goto loop repeat (until FSR = H’79’) End
This loop stores 3+register address in each register. Therefore the register at address Reg9 (address H’78’) is equal to H’7b’
