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Quiz 1 for Computer Logic Design | ECE 238L, Quizzes of Electrical and Electronics Engineering

Material Type: Quiz; Class: Computer Logic Design; Subject: Electrical & Computer Engineer; University: University of New Mexico; Term: Fall 2008;

Typology: Quizzes

Pre 2010

Uploaded on 07/22/2009

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ECE 238 - Quiz 1
Name:………………………………………..
Section:………………………………………
Date:…………………………………………
1. Unlike languages such as C or low-level assembly which all run sequentially
one instruction at a time, VHDL can be used to describe concurrent events.
a) True b) False c) Neither
2. VHDL is case sensitive.
a) True b) False c) Neither
3. The entity section is used to declare the ________ of the circuit.
a) Functions
b) Inputs and outputs
c) Behavior
d) Components
4. The SIGNAL statement can be thought of as a _________ inside the device.
a) Port
b) Component
c) Physical wire
d) Entity
5. The architecture section is used to declare the ________ of the circuit.
a) Functions
b) Inputs and outputs
c) Behavior
d) Components
6. Consider the following code:
pf2

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ECE 238 - Quiz 1

Name:……………………………………….. Section:……………………………………… Date:…………………………………………

  1. Unlike languages such as C or low-level assembly which all run sequentially one instruction at a time, VHDL can be used to describe concurrent events.

a) True b) False c) Neither

  1. VHDL is case sensitive.

a) True b) False c) Neither

  1. The entity section is used to declare the ________ of the circuit.

a) Functions b) Inputs and outputs c) Behavior d) Components

  1. The SIGNAL statement can be thought of as a _________ inside the device.

a) Port b) Component c) Physical wire d) Entity

  1. The architecture section is used to declare the ________ of the circuit.

a) Functions b) Inputs and outputs c) Behavior d) Components

  1. Consider the following code:

6.1 Draw its corresponding logic diagram. 6.2 As a hardware description language, the code in lines 19-22 follows a sequential order (i.e., event order follows a textual order).

a) True b) False c) Neither

6.3 Assume that there is a change on the value of the input signal c. Thus,

a) All the statements (line 19 to line 22) are concurrently executed. b) All the statements are sequentially executed. c) All the statements except line 20 are concurrently executed. d) The above options are not correct.

  1. In VHDL, we can write a concurrent statement as:

7.1 Draw the logic diagram for the above VHDL statement. 7.2 Describe the operation of the circuit in part 7.