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Main points of this past exam are: Logic Function, Product Terms, Standard Sum, Sum-Of-Products Form, Implemented Together, Input Logic, Gate Inputs, Combinational Circuit, Two’S Complement, Xor Gates
Typology: Exams
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Final Examination Page 1 of 12 CS 150 - Sp. 96
UNIVERSITY OF CALIFORNIA AT BERKELEY BERKELEY • DAVIS • IRVINE • LOS ANGELES • RIVERSIDE • SAN DIEGO • SAN FRANCISCO SANTA BARBARA • SANTA CRUZ Department of Electrical Engineering and Computer Sciences
CS 150 - Spring 1996 Prof. A. R. Newton
(Open Katz, Calculators OK, 3 hours)
Include all final answers in locations indicated on these pages. Use space provided for all working. If necessary, attach additional sheets by staple at the end. BE SURE TO WRITE YOUR NAME ON EVERY SHEET.
(1) (20pts) (a) Consider the following logic function:
(i) Express the function in Standard Sum-of-Products form.
(ii) Express the function as a PLA table using a minimum number of product terms.
(iii) What is the minimum number of bits of storage required to implement this function using a ROM? How many address lines would be required?
(iv) Implement the function using a two control-line, four input multiplexer and a minimum number of additional logic gates (AND, OR, NAND, NOR, XOR). Assume complements are available and show all working.
1(a) 13pts (i) f(A, B, C, D) = ____________________________________ (ii)
(iii) Number of bits: _________ Number of address lines: _________ (iv)
CS 150 - Sp. 96 Page 2 of 12 Final Examination
(b) Consider the following two functions expressed in Standard Sum-of-Products form:
fa(A,B,C,D) = Σ m (0,1,4,5,9,13,14,15)
fb(A,B,C,D) = Σ m (0,4,5,7,9,13,14,15)
(i) Does fa(A,B,C,D) contain a hazard when implemented in minimum sum-of-products form? If so, what product term should be added to remove it?
(ii) The functions are to be implemented together as a single two-output, four input logic circuit in sum-of- products form. Express each output in sum-of-products algebraic form, where the number of (AND gates+OR gates) needed is minimized. Do not consider the number of gate inputs in your calculation, just the total number of gates, and ignore any hazards (i.e. do not remove them, if present).
1(b) 7pts
(i) Is there a hazard in fa? ________ If so, what would you add? ________________
(ii)
fa(A,B,C,D) = _______________________________
fb(A,B,C,D) = _______________________________
Additional Space for Problem 1
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CS 150 - Sp. 96 Page 4 of 12 Final Examination
2 (b) Derive a combinational circuit for realizing the two’s complement of a four-bit binary number. Use the minimum number of AND, OR, NAND, NOR, and XOR gates only. Assume complements are available.
2(b) (10pts)
Additional Space for Problem2(b)
Final Examination Page 5 of 12 CS 150 - Sp. 96
(3) (20pts)
a “don’t care” for the value of Z:
PS NS, Z x = 0 x = 1
(a) Obtain a reduced state table by eliminating redundant states and by combining equivalent states using the implication chart method. Show your final implication chart and include a final version of the reduced state table with the minimum number of states.
3(a) (10pts)
Implication Chart:
Reduced State Table:
Final Examination Page 7 of 12 CS 150 - Sp. 96
(4) (20pts)
(a) A two-button electrical lock will actuate according to the following sequence:
A: 0 1 1 1 1 0 1 B: 0 0 1 0 1 1 1 Z: 0 0 0 0 0 0 1 Z=1 opens the lock and is the circuit output while A and B correspond to the two buttons. A switch being depressed (pushed and held down) corresponds to a 1 and a switch being released (removing one’s finger from the button) corresponds to a zero. Releasing both buttons clears the circuit and only one button may be pressed or released at a time , as is the case in the above sequence. (i) Obtain a primitive flow table for the circuit. (ii) Obtain a reduced, merged flow table by eliminating any redundant states and by merging equivalent states. Show your merger diagram.
4(a) (10 pts)
Primitive Flow Table:
Merger Diagram: Reduced, Merged Flow Table:
CS 150 - Sp. 96 Page 8 of 12 Final Examination
(b) Consider the merged flow table shown opposite: Perform a race-free state-assignment using as few internal state variables as possible. Indicate all required adjacency constraints and list your final state codes. Be very clear in explaining how you arrived at your result.
4(b) (10pts)
State assignment: _______________________________________________________________
Adjacency constraints:
Additional Space for Problem 4
CS 150 - Sp. 96 Page 10 of 12 Final Examination
(b) (i) Find a hazard-free implementation of the following function using only 3-input NOR gates. Use the minimum number of gates+gate inputs and assume complements are available:
f(A,B,C,D) = Σ m (0,2,6,7,8,10,13)
(ii) Explain how a hazard in the next-state logic of a Mealy clocked synchronous machine can affect the performance of the machine adversely. Consider all cases and recommend ways of avoiding such adverse outcomes (other than simply eliminating the hazard by adding additional gates!) (iii) What are the adverse effects which might result when one eliminates the hazard by adding additional gates?
5(b) (10pts)
(i) Hazard-free, three-input NORs only:
(ii) .......................................................................................................................................................................... .......................................................................................................................................................................... .......................................................................................................................................................................... .......................................................................................................................................................................... .......................................................................................................................................................................... .......................................................................................................................................................................... .......................................................................................................................................................................... .......................................................................................................................................................................... .......................................................................................................................................................................... ..........................................................................................................................................................................
(iii) .......................................................................................................................................................................... .......................................................................................................................................................................... .......................................................................................................................................................................... .......................................................................................................................................................................... .......................................................................................................................................................................... .......................................................................................................................................................................... ..........................................................................................................................................................................
Final Examination Page 11 of 12 CS 150 - Sp. 96
Additional space for Problem 5