Download Quiz 4 for ECE 337 Fall 2008 - Microarchitecture Improvements and Pipelining Stages and more Quizzes Computer Architecture and Organization in PDF only on Docsity!
Name: ECE 337 Fall 2008
Quiz 4 (25 points)
10/31/2007, Friday
- List at least four improvements of Mic-2 over Mic-1 microarchitecture. (4 points)
–Remove decoder to speed execution –Reduce interpreter loop with microcode –Three bus architecture –Instruction fetch unit
- How many stages exist in the pipelined data path in Mic-3 microarchitecture? What are they? (4 points)
There are four-stage pipeline in Mic-3. Instruction Fetch Unit ALU Input Buses ALU/Shifter ALU Output Bus
- How many stages exist in Mic-4 microarchitecture? What are they? What is the difference between the control store of Mic-3 and Mic-4? (8 points)
There are seven-stage pipeline in Mic-4. Three of them are in the control unit, four of them are in the data path.
Instruction Fetch Unit Decoding Unit Queuing Unit ALU Input Buses ALU/Shifter ALU Output Bus Write back to Memory
Mic-3 has Compiled Control Store Addresses Mic-4 has Look up Control Store Addresses in two ROMs.
- What is a true dependence or a Read After Write (RAW) dependence in Mic- pipeline implementation? (1 point)
The situation that a microstep cannot start because it is waiting for a result that a previous microstep has not yet produced is called true dependence or a RAW dependence.
- Write microcode for the Mic-2 to implement the JVM instruction DSTORE i, which puts the value at next-to-top of stack into local variable i and puts the value at the top-of- stack into variable i+1. (Hint: you can start with the microcode for the Mic-2 to implement ISTORE i ) (8 points)
One possible solution is:
dstore 1 MAR = MBR1U + LV + 1 // local variable i+1 location dstore 2 MDR = TOS, wr // save the top-of-stack data to local //variable i+ dstore 3 MAR = SP = SP-1, rd // SP point to the next-to-top, read // data from next-to-top dstore 4 (empty) dstore 5 MAR = MBR1U + LV; wr // data from next-to-top is saved to // local variable i dstore 6 MAR = SP = SP-1, rd // update SP and TOS dstore 7 (empty) dstore 8 TOS = MDR; go to (MBR1)
