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COMPUTER ARCHITECTURE AND
ORGANIZATION: An Integrated Approach
PRACTICE PROBLEMS
(Solutions are at the end) FEBRUARY 2007
CHAPTER 1 PROBLEMS
(1-1) Place the computing technologies in the proper chronological order corresponding to when they were first introduced, from earliest to most recent:
- integrated circuits
- mechanical - machine powered
- mechanical - manually powered
- transistors
- vacuum tubes
CHAPTER 2 PROBLEMS
(2-1) The binary representation of the hexadecimal number 3B7F is (choose one):
(A) 0100 1001 1110 1101 (B) 0011 1011 0111 1111 (C) 0010 0100 0000 1010 (D) 0110 0011 1011 1100 (E) 1101 1100 1011 0101
(2-2) Convert the following numbers as indicated.
(a) (110101) 2 to unsigned base 10. (b) (−29) 10 to two’s complement (use 8 bits in the result). (c) (61543) 8 to unsigned base 16 (use four base 16 digits in the result). (d) (37) 10 to unsigned base 3 (use four base 3 digits in the result).
(2-3) A computer with a 32-bit word size uses two's complement to represent numbers. The range of integers that can be represented by this computer is:
(A) –2^32 to 2 32 (B) –2 31 to 2^32 (C) –2 31 to 2^31 – 1 (D) –2^32 to 2 3 (E) –2^32 – 1 to 2 32
(2-4) Computer A uses the following 32-bit floating-point representation of real numbers:
S Mantissa Exponent 31 30 7 6 0
Computer B uses the following floating point representation scheme:
S Mantissa Exponent 31 30 8 7 0
Which of the following statements is true with regard to Computer B’s method of representing floating-point numbers over Computer A’s method? (A) both the range and precision are increased (B) the range is increased but the precision is decreased (C) the range is decreased but the precision is increased
(D) both the range and precision are decreased (E) both the range and precision remain the same
(2-5) (ref: Stallings, 1999) A normalized floating point representation has an exponent e with a representation that lies in the range 0 ≤ e ≤ X , in excess q , with a base b and a p digit fraction. Note the emphasis on representation , as opposed to value.
(a) What are the largest and smallest positive values that can be represented? (b) What are the largest and smallest gaps? (c) What is the number of representable numbers?
(2-6) Express -1/32 in the IEEE 754 single precision format.
(2-7) For parts (a) through (d), use a floating point representation with a sign bit in the leftmost position, followed by a three-bit excess 4 exponent, followed by a normalized six-bit fraction in base 4. Zero is represented by the bit pattern 0 000 000000.
(a) What decimal number is represented by the bit pattern: 1 100 010000? (b) Show the bit pattern for the smallest non-zero positive representable number. (c) Show the bit pattern for the largest positive representable number. (d) There are a total of 10 bits in this floating point representation, so there are 2^10 = 1024 unique bit patterns. How many of these bit patterns are valid? (Remember: 0 = 0 000 000000).
(2-8) Represent (107.875) 10 in the IEEE-754 single precision floating point representation which has a sign bit, an eight-bit excess 127 exponent, and a normalized 23-bit significand in base 2 with a hidden 1 to the left of the radix point. Truncate the fraction if necessary by chopping bits as necessary. Show your work.
CHAPTER 4 PROBLEMS
(4-1) Which of the following operations does function baz in the ARC program shown below carry out? The parameters A and B are passed to the function and returned from it are passed via the stack. B is closer to the stack pointer than A. Circle one of these operations:
(A) min ( A , B ) (B) max ( A , B ) (C) addcc ( A , B ) (D) subcc ( A , B )
(E) ( A == B ) <--- in this case, the result is a boolean, indicated by a nonzero result.
baz: ld %sp, 4, %r ld %sp, 0, %r orncc %r2, %r0, %r addcc %r3, 1, %r addcc %r1, %r3, %r bneg foo st %r2, 4, %sp ba DONE foo: st %r1, 4, %sp addcc %r14, 4, %r DONE: jmpl %r15, 4, %r
(4-2) The memory map for a video game that can accept two game cartridges is shown below. Each 32-bit word is composed of four 8-bit bytes in a big endian format, just like the ARC.
Reserved for built-in graphics routines
Plug-in game cartridge #
I/O space
Stack pointer System Stack
Top of stack
Bottom of stack
Screen Flash Joystick x Joystick y
224 – 4
32 bits
Address Data
byte 2 24 – 1
Plug-in game cartridge #
(a) How large can the stack grow, in bytes? (Leave your answer as an equation in powers of two, e.g. 8 + 2 10 .)
(b) When a joystick is moved, the horizontal (joy_x) and vertical (joy_y) positions of the joystick are updated in memory locations (FFFFF0) 16 and (FFFFF4)16, respectively. When the number ‘1’ is written to memory location (FFFFEC) 16 the screen flashes, and then location (FFFFEC) 16 is automatically cleared to zero by the hardware (the software does not have to clear it). Write an ARC program that flashes the screen every time the joystick moves. Use the skel- eton program shown below. The ARC instruction set is summarized at the end of the exam. .begin ld [joy_x], %r7! %r7 and %r8 now point to the ld [joy_y], %r8! joystick x and y locations ld [flash], %r9! %r9 points to the flash location loop: ld %r7, %r1! Load current joystick position ld %r8, %r2! in %r1=x and %r2=y ld [old_x], %r3! Load old joystick position ld [old_y], %r4! in %r3=x and %r4=y orncc %r3, %r0, %r3! Form one’s complement of old_x addcc %r3, 1, %r3! Form two’s complement of old_x addcc %r1, %r3, %r3! %r3 <- joy_x - old_x be x_not_moved! Branch if x did not change ba moved! x changed, so no need to check y x_not_moved:! Your code starts here, about four lines. orncc %r4, %r0, %r4! Form one’s complement of old_y addcc %r4, 1, %r4! Form two’s complement of old_y addcc %r2, %r4, %r4! %r4 <- joy_y - old_y be loop! Repeat ! This portion of the code is entered only if joystick is moved. ! Flash screen; store new x,y values; repeat.
moved: <— YOUR CODE GOES HERE
flash: #FFFFEC! Location of flash register joy_x: #FFFFF0! Location of joystick x register joy_y: #FFFFF4! Location of joystick y register old_x: 0! Previous x position old_y: 0! Previous y position .end
(4-3) With regard to stack frames, a main routine (or method, for Java) is treated just like any other routine or method. Show the stack frame for main() in the diagram below. Fill in the blanks for the main() stack frame with one-word descriptions of what is stored in each location. Note that there are many correct solutions (and many incorrect solutions too.)
CHAPTER 5 PROBLEMS
(5-1) List the microinstructions that are executed in interpreting the ARC "st %r1, %r2, %r3" instruction. Start with microinstruction 0. Just list the microinstruction numbers, not the code.
(5-2) Write the binary form for the microinstructions shown below. Use the value 0 for any fields that are not needed.
1615: R[temp1] ← R[rs1]; GOTO 21; 21: R[temp2] ← NOR(R[temp0], R[temp0]);
R D
W A B C R ALU COND JUMP ADDR
A M U X
B M U X
C M U X
60:
(5-3) Microcode: An ALU that operates on 8-bit operands can be implemented with a read-only memory (ROM) that behaves as a lookup table (LUT), in which the data and control bits are treated alike. The block diagram shown below illustrates the external behavior of the ALU that we would like to implement with a ROM LUT. The A and B lines are for the operand inputs, and the F lines (that is, the control inputs) select the ALU function according to the truth table shown below. The Cin and Cout lines are for the carry in and the carry out, respectively. The carry out is always 0 when an addition is not taking place. The 8-bit output appears on the Z lines. Assume that a two’s complement representation is used. Fill in the missing entries in the truth table below. [HINT: The solution for the first row is all 1's for Z 7 - Z 0 .]
0 0 1 1
0 1 0 1
NOR Multiply AND Add
F 1 F 0 Function ROM LUT
8
8
Cin
1
2
8^ Z^7
Cout
1
Z 0
.. .
A 7
A 0
.. . Data out lines B 7
B 0
.. .
F 1 F 0
Address lines
A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 B 7 B 6 B 5 B 4 B 3 B 2 B 1 B 0 C in F 1 F 0 Z 7 Z 6 Z 5 Z 4 Z 3 Z 2 Z 1 Z 0 C out 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 _ _ _ _ _ _ _ _ 0 _ _ _ _ _ _ _ _ 0 0 0 0 0 0 1 1 0 0 1 0 0 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 _ _ _ _ _ _ _ _ _
CHAPTER 6 PROBLEMS
(6-1) Translate the following Pascal code into SPARC (note: this is a variation of a problem from the Tanenbaum Structured Computer Organization textbook).
/* Compute min of i and j / function min (i, j: Int): Int / i and j are parameters, min returns Int/ var m: Int; begin if i < j then m := i else m := j; min := m / This is how a Pascal function returns a value */ end;
(6-2) Translate the single line indicated in the following ARC code into object code. Remember: branch displacements are in terms of 4-byte words, not bytes. (That is, an offset of 8 bytes is represented as 2, because it is equivalent to an offset of 2 words.)
.begin .org 0
srl %r2, 10, %r2 ans: 10 00010 100110 00010 1 0000000001010
(6-3) Disassemble the following ARC object code into a source statement. Since there is not enough information in the object code to determine symbol names, use numbers (offsets, like +5 or −12) instead, if needed.
00000010 10000000 00000000 00000011
(6-4) Given the assembly language program shown on the next page, which uses an assembly language syntax that should be new to you, construct a symbol table. As with the ARC assembly language, each instruction in this assembly language occupies four bytes. Not all of the lines in the table will be needed. Do not try to figure out what the program does – it is not helpful to know this. Mark any undefined symbols with an “X.” All values are given in base 10. Registers are named R0, R1, and R
(6-7) Given an architecture that implements the following instructions:
Mnemonic Operand(s) Meaning PUSH arg Push contents of memory location arg onto stack POP arg Pop stack into memory location arg BA label Branch to label ADD arg1, arg2, arg3 arg3 <- arg1 + arg
What is the result of executing the following program?
PUSH A
ADD A, 1, A
PUSH A
ADD A, 1, A
PUSH A
POP B
ADD B, -1, B
POP B
ADD B, -1, B
POP B
(6-8) A program is running on a pipelined computer in which every fourth instruction is a jump (or a branch), and there is a 20% probability that each jump is taken. When a jump is taken, the pipeline is flushed, which has a branch penalty of 3. Compute the average instruction time in terms of instruction cycles.
(6-9) Consider the following code segment, which is for an architecture that many be new to you (the MIPS): LW R1, 0(R2) Load a word from memory SUB R1, R1, R3 Subtract BEQZ R1, L Branch if equal to zero OR R4, R5, R6 or . . .
L: ADD R7, R8, R9 Add
There is a load delay slot after the load from memory instruction: LW. The dependence of the subsequent SUB and BEQZ instructions on the LW instruction means that we need a stall after LW. Suppose we know that the branch is almost always taken, and that the value of R7 is not needed on the fall-through path. Suggest a rescheduling of the code segment which would increase the speed of the program.
CHAPTER 7 PROBLEMS
(7-1) A cache has a 95% hit ratio, an access time of 100ns on a cache hit, and an access time of 800ns on a cache miss. Compute the effective access time.
(7-2) (From Stallings, 1999) A set associative cache consists of 64 slots divided into 4-slot sets. Main memory contains 4K blocks of 128 words each. Show the format of the main memory address.
(7-3) Using the page table shown below, translate virtual address 2050 into a physical address, and translate physical address 25 into a virtual address. Address length is 16 bits, page size is 2048 words. Physical memory has 4 page frames.
Page Present (1-in/0-out) Page Frame 0 1 3 1 1 2 2 1 0 3 0 -- ...
(7-4) A computer has 16 pages of virtual address space but only 4 page frames. Initially the memory is empty. A program references the virtual pages in the order: 0 2 4 5 2 4 3 11 2 10.
(a) Which references cause a page fault with the LRU page replacement policy? (b) Which references cause a page fault with the FIFO page replacement policy?
(7-5) When running a particular program with N memory accesses, a computer with a cache and paged virtual memory generates a total of M cache misses and F page faults. T1 is the time for a cache hit; T2 is the time for a main memory hit; and T3 is the time to load a page into main memory from the disk.
(a) What is the cache hit ratio?
(b) What is the main memory hit ratio? That is, what percentage of main memory accesses do not generate a page fault?
(c) What is the overall effective access time for the system?
(7-6) Four 256-word × 8-bit PROM chips are used to produce a total capacity of 1024-word × 8-bits. How many address bus lines are required? (Circle one.) (A) 4 (B) 8 (C) 10 (D) 16 (E) 32
(7-7) A direct mapped cache consists of 4 blocks of 16 words per block. Main memory contains 32K blocks of 16 words each. The hit time for a cache access is 10 ns, and the miss time is 200 ns, which includes the time to transfer the missed block from the main memory to the cache. Note: When referring to memory, 1K = 1024. Compute the hit ratio for a program that loops 10 times from locations 0 – 64.
(7-8) A set associative cache consists of 64 slots divided into 4-slot sets. Main memory contains 4K blocks of 128 bytes each. Show the format of the main memory address. (Tag, Slot or Set, and Byte fields.)
Present bit Page #
0 1 2 3 4 5 6 7 0 0 1 0 1 0 1 0 xx xx 00 xx 01 xx 11 xx
Disk address
Page frame field
01001011100 11101110010 10110010111 00001001111 01011100101 10100111001 00110101100 01010001011
(a) What is the main memory address for virtual address 1024? (b) What is the virtual address for main memory address 512?
(7-13) A memory has 2^24 addressable locations. What is the smallest width in bits that the address can be while still being able to address all 2^24 locations?
(7-14) If a virtual memory system has 4 pages in real memory and the rest must be swapped to disk, determine the hit ratio for the following page address system. Assume memory starts empty. Use the First In First Out (FIFO) page replacement policy. Choose the closest answer.
PAGE REQUESTS: 2 5 3 4 1 4 7 2 1 3 1 7 4 5 4 6
(A) 10% (D) 31%
(B) 15% (E) 50%
(C) 25%
(7-15) A memory system has a two-level cache in which Level 1 is closer to the CPU than Level 2. The hit time for the Level 1 cache is T1 and the hit time for the Level 2 cache is T2. The miss time for the Level 2 cache is T3. On a cache miss at either level, the miss time includes the time to read in a block and deliver the requested word. What is the effective access time of the memory system if the hit ratios of both caches are 90%? An equation for the effective access time of a two-level cache is shown below:
TEFF =
(No. on±chip cache hits) (Time per on±chip cache hit) + (No. off±chip cache hits) (Time per off±chip cache hit) + (No. off±chip cache misses) (Time per off±chip cache miss) Total number of memory accesses
CHAPTER 8 PROBLEMS
(8-1) A hard magnetic disk with a single platter rotates once every 16 ms. There are 8 sectors on each of 1000 tracks. An interleave factor of 1:2 is used. What is the fastest possible time to copy a track from the top side of the platter to the corresponding track on the bottom side of the platter? Assume that the sectors must be read in numerical order starting from 0, that the top and bottom
tracks must be mirror images, that any number of sectors can be read from the top track before writing them to the bottom track, and that simultaneous reading and writing is not allowed (even on different tracks.)
(8-2) Consider a disk drive with the following characteristics:
7200 revolutions per minute rotation speed 7 msec average seek time 256 sectors per track, with 512 bytes per sector 2048 tracks per surface 16 surfaces 1 head per surface, all heads move together as a group reading and writing cannot be done at the same time
(a) What is the total capacity of the disk drive? (b) What is the data transfer rate in bytes per second for this drive? That is, once the head is positioned over the sector to be read, what is the data transfer rate? (c) What is the average time to transfer a whole sector from one track to another track?
(8-3) A number of disks, a CPU, and the main memory are all connected to the same 10 MHz 32-bit bus. The disk has a transfer rate of 2 MBytes/sec. The CPU and main memory can both keep pace with the bus. How many disks can be simultaneously transmitting?
CHAPTER 9 PROBLEMS
(9-1) Construct an SEC code for EBCDIC ‘T’. When constructing the code, number the bits from right to left starting with 1 (the same way it is done in the book).
(9-2) Construct the SEC code for the Unicode character ‘1/4’ = 00BC 16 using even parity. Hint: check bits go in positions that correspond to powers of 2.
(9-3) If 7-digit telephone numbers are assigned so that misdialing one digit results in an unassigned number, how many numbers can be assigned?
(9-4) For SEC of 7-digit phone numbers, we need to add check digits such that the Hamming distance(H.D.) is 3 (for error correction of p digits, we need H.D. = 2 p +1. For SEC, p =1 so H.D. is 3). How many check digits should we add?
(9-5) In alphabetic encryption (AE), a string of characters is mapped into a different, longer string of characters consisting of only upper case letters. The AE code is shown below:
Letter Code Letter Code Letter Code A 00000 J 01001 S 10010 B 00001 K 01010 T 10011 C 00010 L 01011 U 10100 D 00011 M 01100 V 10101 E 00100 N 01101 W 10110 F 00101 O 01110 X 10111 G 00110 P 01111 Y 11000 H 00111 Q 10000 Z 11001 I 01000 R 10001
(A-3) Design a binary-to-Gray code converter using an 8-to-1 MUX, a 4-to-1MUX, and a 16-to- MUX. Use the truth table shown below:
x2 x1 x0 | z2 z1 z ---------+--------- 0 0 0 | 0 0 0 0 0 1 | 0 0 1 0 1 0 | 0 1 1 0 1 1 | 0 1 0 1 0 0 | 1 1 0 1 0 1 | 1 1 1 1 1 0 | 1 0 1 1 1 1 | 1 0 0
(A-4) Design a circuit that implements function p below using AND, OR, and NOT gates. DO NOT change the form of the equation. The circuit should implement this function exactly.
f(i 0 , i 1 , i 2 ) = i 2 (i 0 i 1 + i 0 i 1 )
(A-5) Label and connect the MUXes shown below to implement function F:
F
F(A,B,C,D) = AB(CD + CD) + AB(CD) + AB(CD + CD)
(A-6) The black box in the following figure consists of a combinational logic unit that uses only AND, OR, and NOT gates.
Black Box (^) f(x, y, z)
x y z
The function f(x, y, z) = 1 whenever x, y are different and 0 otherwise. Which of the following equations leads to the correct design for the combinational logic unit? The prime symbol (') in X' has the same meaning as an overbar. (A) x'y + xy' (B) x + y'z (C) x'y'z' + xy'z (D) xy + y'z + z' (E) x'z + xy + y'z'
(A-7) How many distinct Boolean functions of 3 variables are there? This question is not asking how many possible unique combinations of 3 variables there can be, but rather, how many unique functions of those 3 variables can there be?
(A) 16 (B) 64 (C) 256 (D) 512 (E) 1024
(A-8) Create a state transition diagram that outputs a 1 whenever the sequence of two-bit inputs 00 → 01 *→11 is detected. The asterisk means that the bit-pair 01 can appear any number of times at that position in the sequence, including not at all (zero times). Show the state transition diagram only (do not create a state table or draw a circuit).
(A-9) Design a finite state machine (FSM) that has two control lines C 0 and C 1. The FSM has an output Z that is a 1 if C 1 C 0=00, a 0 if C 1 C 0=01, the value of its current output if C 1 C 0=10, and the complement of its current output if C 1 C 0=11. Just draw a state transition diagram that describes the behavior of the FSM.
(A-10) For the FSM described by the state table shown below,
(a) What is the smallest number of flip-flops needed to implement the FSM? (Do not apply any state reduction techniques.) (b) How many Boolean functions need to be created to implement this FSM? That is, how many next-state and output functions are there?
(A-11) Design a sequential machine that outputs a 1 when the last three inputs are 011 or 110. Note that sequences can overlap, so that an input sequence of 0110 will produce an output sequence of
- Just show the state transition diagram. Do not reduce the diagram or draw a circuit.
(A-12) Given the state transition diagram shown below, design a circuit for this state machine using D flip-flop(s) and one 4-to-16 decoder with OR gates. For the state assignment, use the bit pattern that corresponds to the position of each letter in the alphabet, starting from 0 ( A = 000, B = 001, C = 010, etc. ).
(A) D 1 = Q 1 'Q 2 'Q 3 ' D 2 = Q 1 ' D 3 = Q 2
(B) D 1 = Q 2 Q 3 ' D 2 = Q 1 Q 2 ' D 3 = Q 1 Q 2 Q 3 '
(C) D 1 = Q 1 + Q 2 D 2 = Q 1 ' D 3 = Q 1 Q 2
(D) D 1 = Q 1 'Q 2 Q 3 ' D 2 = Q 1 'Q 2 'Q 3 ' + Q 1 'Q 2 Q 3 ' D 3 = Q 1 Q 2 Q 3 ' + Q 1 'Q 2 'Q 3
(E) D 1 = Q 1 Q 2 Q 3 ' D 2 = Q 1 'Q 2 'Q 3 ' + Q 1 'Q 2 'Q 3 ' D 3 = Q 1 'Q 2 Q 3 '
(A-15) Design a control unit for a simple hand-held video game in which a juggler on the display catches objects. Treat this as an FSM problem, in which you only show the state transition diagram. Do not show a state table, state assignment, or a circuit. The input to the control unit is a two-bit vector in which 00 means “Move Left,” 01 means “Move Right,” 10 means “Do Not Move,” and 11 means “Halt.” The two-bit output Z is 11 if the machine is currently halted, and is 00, 01, or 10 otherwise, corresponding to the input patterns 00, 01, and 11. That is, the two-bit output is identical to the two-bit input, except when the machine is halted, in which case the output is 11 regardless of the input. Once the machine is halted, it must remain in the halted state indefinitely. Show only the state transition diagram.
SOLUTIONS
CHAPTER 1 SOLUTIONS
(1) mechanical - manually operated (2) mechanical - machine powered (3) vacuum tubes (4) transistors (5) integrated circuits CHAPTER 2 SOLUTIONS
(2-1) (B) 0011 1011 0111 1111
(a) 53 (^10) (b) 11100011 2 (c) 6363 (^16)
(d) 1101 3
(2-3) (C) –2 31 to 2 31 – 1
(2-4) (B) the range is increased but the precision is decreased
(2-5) (a) Smallest = .1 × b -q Largest = (1 - b -p ) × b (X - q) (b) Smallest gap = b -p^ × b -q Largest gap = b -p^ × b (X - q ) (c) 2 × (X + 1) × (b - 1) × b p-1^ + 1
(2-6) 1 0 1 1 1 1 0 1 0. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S Exponent Fraction
1/32 = (.00001) 2 = 1.0 x 2-5^. The 1 to the left of the radix point is dropped, which is why the fraction is all 0's. The exponent is in excess 127 (not 128), so -5+127 = 122 for the exponent.
(2-7) (a) –.1 4 × 4 4-4^ = –.25 10
(b) 0 000 010000 (c) 0 111 111111 (d) 2 (sign bit) × 23 (exponent) × 3 (first digit) × 42 (remaining digits) + 1 (zero) = 769
