PowerPC 750-Advance Computer Architecture-Lecture Slides, Slides of Advanced Computer Architecture

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Today’s Topics

Case Studies

 Power PC 750 Architecture

 Power PC 970 Architecture

 Intel Pentium – VI Architecture

Summary

PowerPC 750 - General

PowerPC 750 is an implementation of PowerPC microprocessor family of reduced instruction set computer (RISC) microprocessors

750 implements the 32-bit portion of the PowerPC architecture

It provides 32 - bit effective addresses for:

- Integer data types of 8, 16, and 32 bits - Floating-point data types of 32 and 64 bits

PowerPC Instructions

Instructions are encoded as single-word (32-bit)

Instruction formats are consistent among all instruction types, permitting efficient decoding to occur in parallel with operand accesses

This fixed instruction length and consistent format greatly simplifies instruction pipelining

Integer instructions are:

Integer arithmetic, Integer compare, logical, rotate and shift

PowerPC Instructions … Cont’d

Floating-point instructions are:

Floating-point arithmetic, multiply/add, rounding and conversion, compare, status and control instructions

Load/store instructions are:

Integer and Floating-point load and store; and atomic memory operations (lwarx and stwcx) instructions

PowerPC 750 Block Diagram

PowerPC 750 Block Diagram

Branch IF Processing

DISPATCH Registers Instruction & Rename Buffer Cache (L1) Reservation Stations EXE L2 Cache Interface COM Data Cache (L1)

PowerPC 750: Instruction Flow (decode/dispatch)

Fetch: Maximum 4 inst per cycle Instruction Queue BranchProcessing Unit BPU)

Dispatch Unit Max. 2 Inst/cycle; I Inst/unit Completion QueueAssignment ReservationStations

Store Queue Complete Completion Queue

PowerPC 750 – Instruction Fetch .. Cont’d

However, the number of clock cycles necessary to request instructions from the memory system depends on where exactly is the:

1. branch target instruction cache
2. on-chip instruction L1 cache
3. L2 cache Having understood the instruction let us discuss how the PowerPC decodes and dispatch the instruction

PowerPC 750 – Decode/Dispatch

Note that to facilitate dispatch:

- There must be a vacancy in the specified execution unit - A rename register must be available for each destination operand specified by the instruction - There must be an open position in the completion queue; If no entry is available, the instruction remains in the IQ.

PowerPC 750: Superscalar Pipeline

Maximum four instruction fetch per clock cycle Maximum three instructions dispatch per clock cycle

Maximum three instructions completion per cycle

PowerPC 750 – Execution Units

Furthermore, there exist

• One three-stage floating point unit (FPU) that allows both single- and double-precision operations
• Hardware support for demoralized numbers and Single-entry reservation station are provided
• Thirty-two 64-bit FPRs for single- or double- precision operands

PowerPC 750 – Execution Units …..Cont’d

Two-stage LSU (Load/Store Unit) contains

- Two-entry reservation station - Single-cycle, pipelined cache access - Three-entry store queue

Supports both big- and little-endian modes

It’s dedicated adder performs (extended addition) EA calculations

It performs alignment and precision conversion for floating-point data and sign extension for integer data

PowerPC 750 Completion Unit

Monitors all dispatched instructions and retires them in order

Tracks unresolved branches and flushes instructions from the mispredicted branch

Retires as many as two instructions per clock

PowerPC 750 Rename Buffers

750 provides rename registers for holding instruction results before the completion commits them to the architected register

Refer to the instruction flow diagram again and note that there are six GPR rename registers, six FPR rename registers, and one each for the CR, LR, and CTR

When an instruction is dispatched to its execution unit, a rename register for the results of that instruction is assigned