

















Study with the several resources on Docsity
Earn points by helping other students or get them with a premium plan
Prepare for your exams
Study with the several resources on Docsity
Earn points to download
Earn points by helping other students or get them with a premium plan
Community
Ask the community for help and clear up your study doubts
Discover the best universities in your country according to Docsity users
Free resources
Download our free guides on studying techniques, anxiety management strategies, and thesis advice from Docsity tutors
This course focuses on quantitative principle of computer design, instruction set architectures, datapath and control, memory hierarchy design, main memory, cache, hard drives, multiprocessor architectures, storage and I/O systems, computer clusters. This lecture includes: Power, Architecture, Pentium, Case, Studies, register, Instructions, Cache, Fetch
Typology: Slides
1 / 25
This page cannot be seen from the preview
Don't miss anything!
PowerPC 750 is an implementation of PowerPC microprocessor family of reduced instruction set computer (RISC) microprocessors
750 implements the 32-bit portion of the PowerPC architecture
It provides 32 - bit effective addresses for:
- Integer data types of 8, 16, and 32 bits - Floating-point data types of 32 and 64 bits
Instructions are encoded as single-word (32-bit)
Instruction formats are consistent among all instruction types, permitting efficient decoding to occur in parallel with operand accesses
This fixed instruction length and consistent format greatly simplifies instruction pipelining
Integer instructions are:
Integer arithmetic, Integer compare, logical, rotate and shift
Floating-point instructions are:
Floating-point arithmetic, multiply/add, rounding and conversion, compare, status and control instructions
Load/store instructions are:
Integer and Floating-point load and store; and atomic memory operations (lwarx and stwcx) instructions
Branch IF Processing
DISPATCH Registers Instruction & Rename Buffer Cache (L1) Reservation Stations EXE L2 Cache Interface COM Data Cache (L1)
PowerPC 750: Instruction Flow (decode/dispatch)
Fetch: Maximum 4 inst per cycle Instruction Queue BranchProcessing Unit BPU)
Dispatch Unit Max. 2 Inst/cycle; I Inst/unit Completion QueueAssignment ReservationStations
Store Queue Complete Completion Queue
However, the number of clock cycles necessary to request instructions from the memory system depends on where exactly is the:
PowerPC 750 – Decode/Dispatch
Note that to facilitate dispatch:
- There must be a vacancy in the specified execution unit - A rename register must be available for each destination operand specified by the instruction - There must be an open position in the completion queue; If no entry is available, the instruction remains in the IQ.
Maximum four instruction fetch per clock cycle Maximum three instructions dispatch per clock cycle
Maximum three instructions completion per cycle
Furthermore, there exist
Two-stage LSU (Load/Store Unit) contains
- Two-entry reservation station - Single-cycle, pipelined cache access - Three-entry store queue
Supports both big- and little-endian modes
It’s dedicated adder performs (extended addition) EA calculations
It performs alignment and precision conversion for floating-point data and sign extension for integer data
Monitors all dispatched instructions and retires them in order
Tracks unresolved branches and flushes instructions from the mispredicted branch
Retires as many as two instructions per clock
750 provides rename registers for holding instruction results before the completion commits them to the architected register
Refer to the instruction flow diagram again and note that there are six GPR rename registers, six FPR rename registers, and one each for the CR, LR, and CTR
When an instruction is dispatched to its execution unit, a rename register for the results of that instruction is assigned