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Problem 1 – MIPS Instruction Set Architecture (22 pts, 10 mins)
Extending the Immediate Field in MIPS (6 pts) Mark the following statements true or false about executing the MIPS Core instructions from column 1 of the Green Card. If it’s false, give a counterexample.
Assertion Counterexample T F The immediate field of branches is sign extended
T F The immediate field of and immediate (andi) and or immediate (ori) is zero extended.
T F The immediate field of add immediate (addi) and set less than immediate (slti) is sign extended but the immediate field of add immediate unsigned (addiu) and set less than immediate unsigned (sltiu) is zero extended.
Pipelines and MIPS (12 pts) Assume a 5-stage pipeline as in Ch. 6 executing the MIPS Core instructions from column 1 of the Green Card. The following statements could affect the control lines if they were true. Mark them true or false. If it’s false, give a counterexample.
Assertion Counterexample T F All R-format instructions write one of the 32 general purpose registers in the WB stage T F All I-format instructions except branches write one of the 32 general purpose registers in the WB stage T F No J-format instructions write one of the 32 general purpose registers in the WB stage T F All R-format instructions use two of the 32 general purpose registers in the ID stage. T F No I-format instructions read two of the 32 general purpose registers in the ID stage. T F No J-format instructions read any of the 32 general purpose registers in the ID stage.
Pipelines and MIPS Redux
Part A: (2 points) Assume that Mem[100] == 200, $15 == 100
lw $0, 0($15) addu $0, $0, $ sw $0, 100($15)
What is the value stored into location 200 as the result of the code above? ____________
Part B: (2 points) Assume a 5-stage pipeline with forwarding. How does pipeline control ensure proper execution of the code above?
Problem 3 – Performance (19 points, 10-15 minutes) In the following two questions, we will be comparing the performance of two MIPS processors on an application with the following instruction mix. Cycle Latency Lable Operation Frequency Processor A Processor B Integer arithmetic / logical 30% 1 2 Load / Store 30% 2 4 Branch (predicted) 20% 1 1 Branch (mispredicted) 10% 19 10 Floating Point 10% 40 30
Part A: Calculate the CPI of each processor (6 points)
Price/Performance Table Processor Clock Speed Price Processor A 2.8 GHz $ Processor B 2.0 GHz $
Part B: Calculate the MIPS of each processor. (6 points)
Part C: Which of the two processors has the best cost/performance ratio? How could one get a different result without modifying the processors? (7 points)
Problem 4 – Pipeline Performance (15 points, 10 minutes) Your final project is to implement a deep pipelined processor. However, there may be diminishing returns or detrimental effects that come with very long pipelines. Below is a graph of two possible performance curves.
Assume you have the following:
tclk-to-q tsetup tcl
Part A: The main purpose of pipelining is to increase throughput by minimizing tcl per clock cycle. Consider curve A in the graph above. Ignoring clock skew, give an expression for the theoretical maximum effective instructions/sec we will se with infinite pipeline stages. (10 points)
Part B: Now consider the more realistic curve B for processors with long pipelines. Ignoring clock skew and taking into consideration the hardware/software interface, for what reason we might see curve B instead of curve A? (5 points)
Problem 6 – FPGA vs. ASIC (18 points, 15 minutes)
This question gives a set of circumstances. Match the circumstances with the corresponding design aspect. Note that there are some circumstances which can affect multiple aspects of the design process. Select the BEST one. Each design process should only have one circumstance and all circumstances should be assigned.
For each design aspect, check either FPGA or ASIC depending on what the circumstance makes a better case for.
Part A – Circumstances (14 points) a. The device being designed is going to be used in a mixed signal application requiring analog and digital signal processing. b. Custom mask sets cost upward of 1 million dollars. c. Ford motor company needs devices for all air bag deployment systems in car models for years 2005-2007. d. Design requires the expertise of 4 different groups of engineers in your company. e. Analysts expect shift in the marketplace within 6 months. f. Device developed for McDonald’s new “Toy Story 3” happy meal toy. g. Device customer wants parts now but is still waiting for final system specifications.
Design Aspect Circumstance FPGA ASIC Time to Market Pressures ______________ ________ _______ Heterogeneous System Components ______________ ________ _______ Personnel Costs ($/engineer/year/project) ______________ ________ _______ Manufacturing Costs ______________ ________ _______ Production Volume ______________ ________ _______ Specification Flexibility ______________ ________ _______ Final Sales Price ______________ ________ _______
Part B: Come up with an additional circumstance and design aspect and put them in the final line of the table. Describe the circumstance below. This aspect should NOT reasonably fall under any of the other aspects already mentioned. (4 points)
Most modern computers use semaphores for software synchronization. These semaphores are basically variables that must be read, modified, and written back in one atomic operation. To assure that this command is atomic, these semaphores are usually implemented partially in hardware as atomic test-and-set or atomic swap. In this problem, you will be adding the swap instruction.
swap $r1, $r2, $r
The swap instruction uses three registers, $r1 and $r2 as offsets to a base address is $r3. Here is the RTL description of swap. Mem[$r1 + $r3] <-> Mem[$r2 + $r3]
Part A: Explain how the R-type instruction format can be used to support the swap instruction. In the figure below, specify the value of each field. (3 points)
R-type Instruction: Op Rs Rt Rd Shamt Func
CS152, Fall 2004, Midterm 1, Patterson and Lazzaro Part C – Microcode
(16 points)
Below is partially completed microcode for the
swap
instruction. Fill in the missing code.
Label
ALU
SRC1 SRC
ALUDest
Memory
MemReg
PCWrite
Sequencer
MemSrc
RegRb
Fetch
Add
PC
ReadPC
IR
ALU
Seq
DPATCH
Add
PC
ExtShift
Dispatch
rt
Swap
Add
Rs
Rt
Seq
______
Read
Add
Rs
Rt
Read-ALU
_________
______
Read
Add
_____ _____
_________
_________
______
Write
Add
_____ _____
_________
_________
__________
Write
_________
_________
__________
