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FALL 1994
COMPUTER SCIENCES DEPARTMENT
UNIVERSITY OF WISCONSIN—MADISON
PH. D. QUALIFYING EXAMINATION
Computer Architecture
Qualifying Examination
Monday, September 19, 1994
3:30 − 7:30 PM
1240 Computer Sciences
GENERAL INSTRUCTIONS:
- Answer each question in a separate book.
- Indicate on the cover of each book the area of the exam, your code number, and the question answered in that book. On one of your books list the numbers of all the questions answered. Do not write your name on any answer book.
- Return all answer books in the folder provided. Additional answer books are available if needed.
SPECIFIC INSTRUCTIONS:
Answer all of the following six questions. The questions are quite specific. If, however, some confusion should arise, be sure to state all your assumptions explicitly.
POLICY ON MISPRINTS AND AMBIGUITIES:
The Exam Committee tries to proofread the exam as carefully as possible. Nevertheless, the exam some- times contains misprints and ambiguities. If you are convinced a problem has been stated incorrectly, men- tion this to the proctor. If necessary, the proctor can contact a representative of the area to resolve prob- lems during the first hour of the exam. In any case, you should indicate your interpretation of the problem in your written answer. Your interpretation should be such that the problem is nontrivial.
1. Fast Multipliers You are to design the logic for a high-speed multiplier to multiply two 8-bit numbers. (High- speed multipliers typically use carry-save adders.)
(a) Present the design of such a multiplier. In your design show the logic-level design of each building block, and how the building blocks are used to construct the final multiplier. (It is sufficient to specify the logic-level design using Boolean equations.)
(b) Estimate the total number of gates (which type, and how many inputs) in your multiplier.
(c) Estimate the delay through your multiplier, in terms of gate delays.
2. Disk Technologies Spin-Quick Disk Industries is perfecting their design for a new 1.2 inch diameter hard disk drive for lap-top and palm-top computers. This new disk has one double-sided platter, with 2, tracks per inch and 20,000 bits per inch (per track). The drive motor hub occupies the center of the platter and has a diameter of 0.6 inches.
For this disk, answer the following questions. Your answers can be arithmetic expressions, or reduced to a single number.
(a) Assume the sector descriptor (sector number) requires 150 bits, the minimum interrecord gap is 200 bits, the sector data size is 4 kilobytes, and the error correcting code for the sec- tor data is 48 bytes. How many sectors can fit on the innermost track? On the outermost track?
(b) What is the capacity of this disk if all tracks have the same number of sectors? ESTIMATE the capacity of the disk if instead it uses "constant bit density", which allows the number of sectors to vary from track to track.
(c) Assume that when seeking, it takes 2 ms to start the head moving, 0.02 ms per track, and 2 ms to stop and stabilize the head once it arrives at the destination track. What is the mean seek time assuming uniform random accesses?
(d) How fast must the disk spin to achieve a mean rotational latency of 2 ms (assume uniform random accesses)?
(e) Given your answers to parts (c) and (d), what is the total mean access time to transfer a 4 kilobyte sector? INCLUDE ONLY THE FACTORS DISCUSSED SO FAR.
5. Hardware support for multiprocessor synchronization Parallel machines often provide hardware support explicitly to facilitate interprocessor synchroni- zation.
(a) Describe the functionality, intended usage, and implementation of the synchronization hardware provided by the following machines:
i) the Sequent Balance (the SLIC chip),
ii) the Thinking Machines CM-5 (the control network), iii) the NYU Ultracomputer.
(b) Compare and contrast the utility of these mechanisms for different programming paradigms, for example, shared memory and data parallel.
6. Cache Memories Caches are typically indexed with the least significant address bits of the block number and use the higher order bits for tags. Computers with paged virtual memory translate virtual addresses into physical addresses. Caches in such computers can use virtual addresses for both tags and indexes (VT/VI) or physical addresses for both (PT/PI).
(a) Compare and contrast VT/VI and PT/PI caches. Be sure to consider in your discussion the effect of cache size, context switches, whether the architecture includes address space identifiers, and whether the cache must support multiprocessor coherence.
(b) Two hybrid caches are also possible: physically-tagged/virtually-indexed (PT/VI) and virtually-tagged/physically-indexed (VT/PI). When might they be used? Compare and contrast them with VT/VI and PT/PI caches and each other.
