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Output Expression - Computer Engineering - Solved Exam, Exams of Computer Science

Main points of this past exam are: Output Expression, Switch-Level Design, Boolean Expressions, Switch Level Implementation, Mixed Logic, Logic Reengineering, Mixed Logic Design, Logic Design, Karnaugh Maps, Prime Implicants

Typology: Exams

2012/2013

Uploaded on 04/08/2013

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ECE 2030 J Computer Engineering Fall 2002
4 problems, 5 pages Exam One Solutions 19 September 2002
1
Problem 1 (2 parts, 20 points) Switch-level Design
Part A (10 points) Transform each of the following Boolean expressions to a form where they can be
implemented using switches (i.e., there should be no bars in the expression except for complements of the
inputs A, B, C, etc.). The behavior of the expression should remain unchanged.
HGFEDCBAOutXโ‹…+โ‹…โ‹…+โ‹…+= )()()( HGFEDCBA +โ‹…โ‹…+โ‹…++=
))(()( EDCCBAOutYโ‹…โ‹…+++= EDCCBA โ‹…++โ‹…โ‹…= [= EDC โ‹…+ ]
Part B (10 points) For each expression below, create a switch level implementation using N and P type
switches. Assume both inputs and their complements are available. Your design should contain no shorts
or floats. Use as few transistors as possible.
C
Outy
D
A
D
B
C
A
B
AB
Outx
A
C
B
C
E
D
ED
OUTx = )())(( EDCBA โ‹…+โ‹…+ OUTy = )( DCBA ++โ‹…
pf3
pf4
pf5

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4 problems, 5 pages Exam One Solutions 19 September 2002

Problem 1 (2 parts, 20 points) Switch-level Design

Part A (10 points) Transform each of the following Boolean expressions to a form where they can be implemented using switches (i.e., there should be no bars in the expression except for complements of the inputs A, B, C, etc.). The behavior of the expression should remain unchanged.

Out (^) X = ( A + B )โ‹…( C + D )โ‹…( E โ‹… F + G )โ‹… H = A^ + B + C โ‹… D + E โ‹… F โ‹… G + H

Out (^) Y = ( A + B + C )+( C โ‹…( D โ‹… E ) ) =^ A^ โ‹… B โ‹… C + C + D โ‹… E [=^ C^ +^ D โ‹… E ]

Part B (10 points) For each expression below, create a switch level implementation using N and P type switches. Assume both inputs and their complements are available. Your design should contain no shorts or floats. Use as few transistors as possible.

C

Out y

D

A

D

B

C

A

B

A B

Out x

A

C

B

C

E

D

D E

OUTx = (( A + B )โ‹… C )+( D โ‹… E ) OUTy = A โ‹…( B + C + D )

4 problems, 5 pages Exam One Solutions 19 September 2002

Problem 2 (3 parts, 32 points) Mixed Logic Reengineering

A B C D E

OUTx

F

G

OUTy

Part A (12 points) Write the output expression for the gate design shown above. Also determine

the number of transistors used in its implementation.

OUTx = (( A + B )โ‹… C )+(( D โ‹… E )โ‹…( F + G ))

OUTy = (^) ( D โ‹… E )โ‹…( F + G )โ‹…( F + G )

transistors: 7 nors * 4 trans/nor + 6 inverters * 2 trans/inverter = 40

Part B (10 points) Reimplement the behavior below with a mixed logic design style using only

NAND gates and inverters. Determine the number of transistors used in this implementation.

A B C D E F G

OUTx

OUTy

transistors: 7 nands * 4 trans/nand + 9 inverters * 2 trans/inverter = 46

Part C (10 points) Reimplement the behavior below with a mixed logic design style using only

OR gates and inverters. Determine the number of transistors used in this implementation.

A B C D E F G

OUTx

OUTy

number of transistors: (^) 7 ors * 6 trans/or + 8 inverters * 2 trans/inverter = 58

4 problems, 5 pages Exam One Solutions 19 September 2002

Problem 4 (3 parts, 18 points) Building Blocks

Part A (5 points) Which building block has the following behavior?

E In 1 In 0 O 3 O 2 O 1 O 0 0 X X 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0

This is the behavior of a 2 -to- 4 decoder.

Part B (10 points) Design an 8-to-1 multiplexor using only pass gates and inverters. Clearly

label all inputs and outputs. How many transistors are in your implementation?

I 0

I 1

I 2

I 3

I 4

I 5

I 6

I 7

s 0

OUT

s 1 s^2

Number of transistors: 3 inverters * 2 trans/inverter + 14 passgates * 2 trans/gate = 34.

Problem 4 Part C (3 points) Design a 1-to-8 demultiplexor using the 8-to-1 mux you designed

MUX

  • 4 problems, 5 pages Exam One Solutions 19 September - 8-to- in part 4B (in icon form). Clearly label the inputs and outputs. - O In - O - O - O - O - O - O - O - I - I - I - I - I - I - I - I
    • 1-to- Out