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The solutions to exam two of the computer engineering class ece 2030 held in spring 2001. The exam covers various topics including converting binary and octal values to decimal and hexadecimal notation, addition of signed numbers using two's complement and unsigned representations, implementing transparent latches, and designing toggle cells for counters.
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4 problems, 4 pages Exam Two Solution 21 March 2001
Problem 1 (3 parts, 30 points) Numbers and Arithmetic
Part A (9 points) Convert some binary values (and powers of two) into decimal notation:
binary notation decimal notation
110.011 4 + 2 + .25 + .125 = 6.
11101100 128 + 64 + 32 + 8 + 4
225 32 Million
Part B (9 points) Convert the following octal values into hexadecimal notation:
octal notation hexadecimal notation
77 111111 = 3F
3546 11101100110 = 766
72.1 111010.001 = 3A.
Part C (12 points) For each problem below, (a) compute the operations using the rules of addition, (b) indicate whether an error occurs assuming all numbers are expressed using a four bit two’s complement representation, and (c) indicate whether an error occurs assuming all numbers are expressed using a four bit unsigned representation.
addition result
signed error?
unsigned error?
4 problems, 4 pages Exam Two Solution 21 March 2001
Problem 2 (3 parts, 28 points) Art of the State
Part A (10 points) Implement a transparent latch using only six two-input NOR gates. Label the inputs In and En , and the output Out. No other gates should be used.
Out
En
In
Part B (8 points) Implement register with write enable using transparent latches, NAND gates, and inverters. Use an icon for the transparent latches. Label the inputs In , WE, ΦΦΦΦ 1 , ΦΦΦΦ 2 and the output Out.
In Out
En
Latch
In Out
En
Latch
In
Out
Part C (10 points) Assume the following signals are applied to your register. Draw the output signal Out. Draw a vertical line where In is sampled. Assume Out starts at zero.
4 problems, 4 pages Exam Two Solution 21 March 2001
Part C (10 points) Now use copies of your toggle cell (in icon form) to build a divide by five counter. This design should include an active high external count enable CE and an active high external clear CLR. Your design should clear if (A) the external clear CLR is high, or (B) the maximum output count is reached and the count enable is high. You do not need to draw in the clock signals.
Ext Clr
Ext CE TE Out Clr
TE Out Clr
TE Out Clr
Problem 4 (4 parts, 12 points) Multiple Choice
Consider four different 32-bit representations: (A) an unsigned integer representation, (B) a twos complement integer representation, (C) a twos complement fixed point representation with sixteen bits on each side of the fixed point, and (D) a floating-point representation with a 23 bit mantissa and an 8 bit exponent. For each quantity below, circle which representation (A, B, C, or D) most accurately represents the quantity (i.e., which representation can represent the value with the smallest error).