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Exam Solutions for ECE 2030 Computer Engineering - Fall 2004 - Problem 1 to 4, Exams of Computer Science

Charotar University of Science and Technology Computer Science

The solutions to exam three of the ece 2030 computer engineering course taught in fall 2004. The solutions cover problems related to toggle cells, divide by five counter, memory systems, barrel shifter, and microcode. Students can use this document to check their understanding of these topics.

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ECE 2030 1:00pm Computer Engineering Fall 2004

4 problems, 4 pages Exam Three Solutions 17 November 2004

1

Problem 1 (2 parts, 24 points) Counters

Part A (12 points) Design a toggle cell using only two transparent latches, two 2-to-1 muxes, and

an inverter. Use icons for the latch and mux. Your toggle cell should have an active high toggle

enable input TE, and an active low clear input -Clear, clock inputs Φ

1

and

Φ

2

, and an output

Out. The -Clear signal has precedence over TE. Label all signals.

In Out

En

Latch

In Out

En

Latch

I

0

I

1

S

Out

I

0

I

1

S

Out

TE CLR Φ1Φ2

“0” Out

Part B (12 points) Now combine these toggle cells to build a divide by five counter. Your

counter should have an external clear, external count enable, and three count outputs O

2

, O

1

, O

0

.

Use any basic gates (AND, OR, NAND, NOR, & NOT) you require. Assume clock inputs to the

toggle cells are already connected. Your design should support multi-digit systems.

CEOut

Clr

Toggle

CEOut

Clr

Toggle

CEOut

Clr

Toggle

O

0

O

1

O

2

Max Count

Ext. CE

Ext. CLR

Partial preview of the text

Download Exam Solutions for ECE 2030 Computer Engineering - Fall 2004 - Problem 1 to 4 and more Exams Computer Science in PDF only on Docsity!

4 problems, 4 pages Exam Three Solutions 17 November 2004

Problem 1 (2 parts, 24 points) Counters

Part A (12 points) Design a toggle cell using only two transparent latches, two 2-to-1 muxes, and

an inverter. Use icons for the latch and mux. Your toggle cell should have an active high toggle

enable input TE , and an active low clear input -Clear , clock inputs Φ 1 and Φ 2 , and an output

Out. The - Clear signal has precedence over TE. Label all signals.

In Out

En

Latch

In Out

En

Latch

I 0

I 1 S

Out

I 0

I 1 S

Out

TE CLR Φ^1 Φ^2

“0” Out

Part B (12 points) Now combine these toggle cells to build a divide by five counter. Your

counter should have an external clear, external count enable, and three count outputs O 2 , O 1 , O 0.

Use any basic gates (AND, OR, NAND, NOR, & NOT) you require. Assume clock inputs to the

toggle cells are already connected. Your design should support multi-digit systems.

CEOut

Clr

Toggle

CEOut

Clr

Toggle

CEOut

Clr

Toggle

O 0

O 1

O 2

Max Count

Ext. CE

Ext. CLR

4 problems, 4 pages Exam Three Solutions 17 November 2004

Problem 2 (3 parts, 26 points) Memory Systems

Part A (10 points) Consider a 256 Mbit DRAM chip organized as 64 million addresses of 4 bit

words. Assume both the DRAM cell and the DRAM chip are square. The column number and

offset concatenate to form the memory address. Using the organization approach discussed in

class, answer the following questions about the chip. Express all answers in decimal.

number of columns Sqrt (2^28 ) = 2^14 =16K

column decoder required ( n to m ) 14 to 16K

type of mux required ( n to m ) 4K to 1

number of muxes required 4

number of address lines in column number 14

number of address lines in column offset 12

Part B (8 points) Consider a 512 Mbyte memory system with 128 million addresses of 4 byte

words using 256 Mbit DRAM chips organized as 64 million addresses by 4 bit words.

word address lines for memory system log(128M) = 27

chips needed in one bank 4 bytes / 4 bits = 8

banks for memory system 128M / 64M = 2

memory decoder required ( n to m ) 1 to 2

DRAM chips required 8 x 2 = 16

4 problems, 4 pages Exam Three Solutions 17 November 2004

Problem 4 (4 parts, 29 points) Microcode

Using the supplied datapath, write a microcode fragments to accomplish the following

procedures. Express all values in hexadecimal notation. You may not need every row in the

table. Use ‘X’ when a value is don’t cared. For maximum credit, complete the description field.

Use only registers 1, 2, 3, and 4.

Part A (8 points) Write a microcode fragment that loads the value of memory location 200

(hexadecimal) into register 2.

# X Y Z rwe im en

im va au en

-a /s

lu en

lf su en

st ld en

st en

r/ -w

m sel

description

1 X X 1 1 1 200 0 X 1 C 0 X 0 0 X 0 R1 <- 200

2 1 X 2 1 0 X 0 X 0 X 0 X 1 0 1 1 R2 <- MEM[R1]

Part B (11 points) Assume the loaded value contains three ten bit packed value (R, G, and B).

Assume R is the least significant word, then G, then B. Assume the most significant two bits are

zeros. Write a microcode fragment that unpacks R, G, and B into R2, R3, and R4 respectively.

The value should be in the lower ten bits; all other bits should be zero.

# X Y Z rwe im en

im va au en

-a /s

lu en

lf su en

st ld en

st en

r/ -w

m sel

description

3 2 X 3 1 1 A 0 X 0 X 1 0 0 0 X 0 R3 <- R2 >> 10

4 3 X 3 1 1 3FF 0 X 1 8 0 X 0 0 X 0 R3 <- R3 && 3FF

(^5) 2 X 3 1 1 14 0 X 0 X 1 0 0 0 X 0 R4 <- R2 >> 20

6 2 X 2 1 1 3FF 0 X 1 8 0 X 0 0 X 0 R2 <- R2 && 3FF

Part C (6 points) Now add the unpacked values R, G, and B together in R2.

# X Y Z rwe im en

im va au en

-a /s

lu en

lf su en

st ld en

st en

r/ -w

m sel

description

7 2 3 2 1 0 X 1 0 0 X 0 X 0 0 X 0 R2 <- R2 + R

8 2 4 2 1 0 X 1 0 0 X 0 X 0 0 X 0 R2 <- R2 + R

Part D (4 points) Now stored the result back to memory location 200 (hexadecimal).

# X Y Z rwe im en

im va au en

-a /s

lu en

lf su en

st ld en

st en

r/ -w

m sel

description

9 1 2 X 0 0 X 0 X 0 X 0 X 0 1 0 1 MEM[R1] <- R

Exam Solutions for ECE 2030 Computer Engineering - Fall 2004 - Problem 1 to 4, Exams of Computer Science

Related documents

Partial preview of the text

Download Exam Solutions for ECE 2030 Computer Engineering - Fall 2004 - Problem 1 to 4 and more Exams Computer Science in PDF only on Docsity!

4 problems, 4 pages Exam Three Solutions 17 November 2004

Problem 1 (2 parts, 24 points) Counters

Part A (12 points) Design a toggle cell using only two transparent latches, two 2-to-1 muxes, and

an inverter. Use icons for the latch and mux. Your toggle cell should have an active high toggle

enable input TE , and an active low clear input -Clear , clock inputs Φ 1 and Φ 2 , and an output

Out. The - Clear signal has precedence over TE. Label all signals.

I 0

I 1 S

I 0

I 1 S

TE CLR Φ^1 Φ^2

Part B (12 points) Now combine these toggle cells to build a divide by five counter. Your

counter should have an external clear, external count enable, and three count outputs O 2 , O 1 , O 0.

Use any basic gates (AND, OR, NAND, NOR, & NOT) you require. Assume clock inputs to the

toggle cells are already connected. Your design should support multi-digit systems.

O 0

O 1

O 2

4 problems, 4 pages Exam Three Solutions 17 November 2004

Problem 2 (3 parts, 26 points) Memory Systems

Part A (10 points) Consider a 256 Mbit DRAM chip organized as 64 million addresses of 4 bit

words. Assume both the DRAM cell and the DRAM chip are square. The column number and

offset concatenate to form the memory address. Using the organization approach discussed in

class, answer the following questions about the chip. Express all answers in decimal.

number of columns Sqrt (2^28 ) = 2^14 =16K

column decoder required ( n to m ) 14 to 16K

type of mux required ( n to m ) 4K to 1

number of muxes required 4

number of address lines in column number 14

number of address lines in column offset 12

Part B (8 points) Consider a 512 Mbyte memory system with 128 million addresses of 4 byte

words using 256 Mbit DRAM chips organized as 64 million addresses by 4 bit words.

word address lines for memory system log(128M) = 27

chips needed in one bank 4 bytes / 4 bits = 8

banks for memory system 128M / 64M = 2

memory decoder required ( n to m ) 1 to 2

DRAM chips required 8 x 2 = 16

4 problems, 4 pages Exam Three Solutions 17 November 2004

Problem 4 (4 parts, 29 points) Microcode

Using the supplied datapath, write a microcode fragments to accomplish the following

procedures. Express all values in hexadecimal notation. You may not need every row in the

table. Use ‘X’ when a value is don’t cared. For maximum credit, complete the description field.

Use only registers 1, 2, 3, and 4.

Part A (8 points) Write a microcode fragment that loads the value of memory location 200

(hexadecimal) into register 2.

Part B (11 points) Assume the loaded value contains three ten bit packed value (R, G, and B).

Assume R is the least significant word, then G, then B. Assume the most significant two bits are

zeros. Write a microcode fragment that unpacks R, G, and B into R2, R3, and R4 respectively.

The value should be in the lower ten bits; all other bits should be zero.

Part C (6 points) Now add the unpacked values R, G, and B together in R2.

Part D (4 points) Now stored the result back to memory location 200 (hexadecimal).