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Binary Codes: Encoders and Decoders - Prof. Edward Bosworth, Study notes of Computer Architecture and Organization

An overview of binary codes, focusing on encoders and decoders. It includes explanations of 2-bit and 3-bit codes, the functioning of encoders and decoders, and the design of a 10-to-4 encoder. The document also discusses issues with encoders and introduces decoders as the opposite of encoders.

Typology: Study notes

Pre 2010

Uploaded on 08/04/2009

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Review of Binary Codes
We now begin a discussion of MSI (Medium Scale Integration) circuits.
MSI chips have complete circuits, built from multiple gates, on a single chip.
Two classes that we study are:
Encoders and Decoders
Multiplexers and Demultiplexers
These devices are based on binary coded input. We review simple binary codes.
2–bit codes: 00 0 3–bit codes: 000 0
01 1 001 1
10 2 010 2
11 3 011 3
100 4
101 5
110 6
111 7
pf3
pf4
pf5
pf8
pf9
pfa
pfd
pfe
pff
pf12
pf13
pf14
pf15
pf16
pf17

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Review of Binary Codes

We now begin a discussion of MSI ( Medium Scale Integration ) circuits. MSI chips have complete circuits, built from multiple gates, on a single chip. Two classes that we study are: Encoders and Decoders Multiplexers and Demultiplexers These devices are based on binary coded input. We review simple binary codes. 2–bit codes: 00 0 3–bit codes : 000 0 01 1 001 1 10 2 010 2 11 3 011 3 100 4 101 5 110 6 111 7

Encoders

Encoders typically have 2 N inputs and N outputs. These are called 2 N –to–N encoders. Typical examples include 4–to–2 encoders (probably not used much) 8–to–3 encoders 16–to–4 encoders Due to the prevalence of decimal arithmetic, we also have 10–to–4 encoders. NOTE: We cannot encode 10 items with 3 bits; we need 4 bits to do this.

Y1 = X2 + X3 + X6 + X

Y0 = X1 + X3 + X5 + X7 + X

The Circuit Diagram for the 10–4 Encoder

The equations: Y3 = X8 + X Y2 = X4 + X5 + X6 + X Y1 = X2 + X3 + X6 + X Y0 = X1 + X3 + X5 + X7 + X The diagram:

Issues with Encoders

In the above encoder, one should note that the input X 0 is not connected to any output. An output of 0000 always implies that button 0 is pushed. Put another way, this circuit does not distinguish between:

  1. No input button pushed

Decoders

Decoders are the opposite of encoders; they are N–to– N devices. Typical examples include 2–to–4 decoders 3–to–8 decoders 4–to–16 decoders Due to the prevalence of decimal arithmetic, we also have 4–to–10 decoders. These are specialized 4–to–16 decoders with six fewer pins. N–to– N decoders have N inputs, labeled X 0 , X 1 , …., XN– 2 N outputs, similarly labeled Y 0 , Y 1 , etc. optionally, an enable line. Decoders come in two varieties: active high and active low. We focus our lectures on active high decoders: the selected output goes to logic 1 the outputs not selected stay at logic 0.

Description of a 3–to–8 Active–High Decoder

This decoder has three inputs: X 2 , X 1 , X 0 eight outputs: Y 0 , Y 1 , Y 2 , Y 3 , Y 4 , Y 5 , Y 6 , Y 7 Its functioning is best described by a modified truth table. X 2 X 1 X 0 Action 0 0 0 Y 0 = 1, all others are 0 0 0 1 Y 1 = 1, all others are 0 0 1 0 Y 2 = 1, all others are 0 0 1 1 Y 3 = 1, all others are 0 1 0 0 Y 4 = 1, all others are 0 1 0 1 Y 5 = 1, all others are 0 1 1 0 Y 6 = 1, all others are 0 1 1 1 Y 7 = 1, all others are 0 This gives rise to the equations:

The Enable Input

Again, in the above circuit one output will always be active. Suppose we want to have a decoder with no outputs active. This is the function of the enable inpu t, often denoted as “E”. In an enabled high decoder, when E = 0 no output is active when E = 1 the selected output is active Here is the circuit diagram for a 2–to–4 decoder with enable input.

Decoders: Circuit Symbols and Truth Tables

We normally draw a decoder as a box, with inputs to the left and outputs to the right. Note that the enable is drawn at the bottom. The truth table for an active–high 2–to–4 decoder that is enabled high follows. Enable X 1 X 0 Y 0 Y 1 Y 2 Y 3 0 d d 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 1 The “d” indicates that when Enable = 0, all outputs are 0 independent of X 0 , X 1

Implementation of SOP Expressions with Active High Decoders

These are the two functions that I have been using for quite some time.

With the decoder approach, it is best to design from the –list expression.

If one has a truth table or canonical SOP expression, it is easier to first convert

to the –list and then proceed with the design.

Here are F1 and F2. F1 = (1, 2, 4, 7) and F2 = (3, 5, 6, 7)

Just connect the numbered outputs into an OR gate and get the function.

Active–Low Decoders

For good reasons, most commercial decoders are active low , and enabled low. For a decoder that is enabled–low and active–low, we have the following: Enable = 1 All outputs are 1; no output is active. Enable = 0 Only the selected output has value 0 (active); all others have value 1 (inactive). Enable X 1 X 0 Y 0 Y 1 Y 2 Y 3 1 d d 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 0 1 1 1 1 1 We may immediately deduce the decoder equations from the truth table just above. Here they are.

Using the Enable Input

Here we use two 2–to–4 decoders to implement a 3–to–8 decoder.

Use a Demultiplexer as a Decoder

A decoder is the same as a demultiplexer with its inputs renamed. In a demultiplexer, the control inputs (here C 1 and C 0 ) determine which output gets the input. To make this a decoder:

  1. Attach the input to Enable
  2. Attach the decoder inputs to the demux control inputs.
  3. The Enable is then sent to the selected output. In our lab simulator, the demultiplexer appears to be active low. Set Enable = 1 causes all of the outputs to be 1. Set Enable = 0 causes the selected output to be 0 causes the other outputs to be 1.

Implementation Example: F2(A, B, C)

Here we want to use a decoder to implement our standard function F2.

F2(A, B, C) = (3, 5, 6, 7)

= (A + B + C)(A + B + C^ )(A + B^ + C)( A^ + B + C)

Here is the specification for the function, expressed in terms of a standard 3–to–8 active–low decoder. We ignore the Enable issue.

One Implementation: Active–Low and NAND

F2(A, B, C) = (3, 5, 6, 7)

Recall that the definition of the function should not depend on the technology used to implement it. F2 = 1 if and only if one (or more) of outputs 3, 5, 6, and 7 is 0. The decoder will insure that no more than one output is 0. This calls for a NAND gate; its output is 1 if any input is 0.