Download CS 150 Quiz #2, Spring 1993: ROM Contents, State Machine Design, Microprogram Execution and more Exams Digital Systems Design in PDF only on Docsity!
CS 150, Spring 1993
Quiz
Problem
1. (25 pts) List the ROM contents in hexadecimal to implement the Moore type FSM shown below. The inputs A.H and B.H are synchronized. The states are assigned in numerical order, e.g. for state S4, Q2Q1Q0=100. (Follow normal state diagram assumptions: an output is not asserted if it is not listed, holding in the same state is implicit, etc.)
Fill in ROM contents in hexadecimal. (Binary answers will receive no credit):
Address Data Address Data Address Data Address Data 0 1
A
B
1A
1B
C
D
1C
1D
E
F
1E
1F
CS 150, Spring 1993 Quiz #2 1
Problem
2. (15 pts) You are given the state table for an FSM and a partial schematic for the state machine. Complete the design of state machine by adding wires and gates as necessary to the multiplexer inputs. Do not make any other changes to the circuit.
Present State Q1 Q
Input EN
Output SIGNAL
Next State Q1 Q 0 0 0 0
- micro-PC OUT OUT12 OUT11 OUT9..10 OUT6..8 OUT3..5 OUT0..
address 15 MEMCS MEMWE load grp 1 load grp 2 output enab ALU func 0x20 1 0 0 NOP SLOAD R3OUT A plus 1 0x21 1 0 0 MARLD NOP R2OUT x 0x22 1 1 1 NOP NOP SOUT x 0x23 1 0 1 NOP NOP SOUT x 0x24 1 0 0 NOP SLOAD R2OUT A plus 1 0x25 1 0 0 NOP R2LOAD SOUT x 0x26 1 0 0 MARLD NOP R3OUT x 0x27 1 1 0 NOP R3LOAD NOP x 0x28 1 0 0 NOP NOP NOP x ALU function table:
ALU operation ALU code ALU operation ALU code Y = A plus B 000 Y = A 100 Y = A plus B plus carry
001 Y = 0 101
Y = A plus 1 010 Y = 1 110 Y = A minus 1 011 Y = -1 111
3a. Determine the register transfer description for the micro-operations corresponding to each line of the micro-program listed above, and fill in the following table:
Register Transfer Description of Microprogram
micro-PC address register transfer description 0x 0x 0x 0x 0x 0x 0x
3b. If R3 is the CPU program counter, and R2 is used as the stack pointer, describe, in 10 words or less, the computer instruction corresponding to the above micro-program:
3c. Complete the timing diagram for the micro-instructions 0x24 through 0x27 (defined in table above). For the Data_Bus, show when the bus is tri-stated, and table what is on the bus, e.g. "r2".
Answer each part independently. The operation of the RAM is similar to the 2114 studied in lab 5. The control signal MEMCS.L is always asserted.
a. Explain, using register transfer notation, the data transfers taking place in each clock cycle.
b. What is the minimum tclock for R2 to be correctly written with the contents of R1? tclock > ___?
c. What is the minimum tclock for R2 to be correctly written with the contents of RAM? tclock > ___?
d. What conditions must be satisfied to ensure that thold for R2 is not violated? thold < ___?
e. What conditions must be satisfied to ensure that the hold time for the RAM is not violated during the write cycle? twritehold < ___?
f. There is a potential bus conflict at the beginning of a memory write cycle if the RAM output becomes tri-stated too late. What condition must be satisfied to avoid a bus conflict at this time?
Problem
5. (10 pts) Design the state diagram for a Mealey FSM with synchronized input W.H and output Y.H. The output Y should be asserted for one clock cycle whenever the sequence 1011 has been input on W. Note that the patterns may be overlapping, e.g. W = ...1011011000... should generate Y = ...0001001000... The machine should start assuming that a "0" has already been input.
Posted by HKN (Electrical Engineering and Computer Science Honor Society)
University of California at Berkeley
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