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DOCUMENT NUMBER
S12MSCANV2/D
©Motorola, Inc., 2001
MSCAN
Block Guide
V02.
Original Release Date: 19 MAY 1998 Revised: 18 SEP 2002
Motorola, Inc.
Revision History
Version
Number
Revision
Date
Effective
Date Author^ Description of Changes
Summary of changes:
- First pass release.
- Started from Rev. 0.9 of the MSCAN12_2 spec. Changes include the following:
- MSCAN enable (CANE) bit added in CANCTL1 register.
- RxCAN, TxCAN pins now available as GPIO on Port CANP0, respectively when MSCAN not enabled.
- Moved the Port CTL register after the PORT and DDR registers in order to place the PORT and DDR registers on an odd word boundary.
- Registers $__20 - $__3C are reserved and will read 0’s and writes will be unimplemented.
- Scan added per the HCS12 DFT document.
- Register and bit names updated per the HCS12 Module Requirements document.
- Converted spec to new TSCS Spec Template (Rev. 3.3) format, organization, and content. Spec was re-organized and some new sections added.
- Separated out customer information into Section 1 and moved all internal only information, i.e. conditional text, into Section 2 per the spec template.
- Cosmetic and clarification changes made.
- Changes to be less specific to the UDR12 world and more applicable to the CDR12 world.
- Eliminated “weasel” words, may and should.
- Rev. 0.9 spec tagging kept in tact with new functions tagged with temporary tags ({AT} - Additional Test, {T} - existing Test).
0.1 5-25-98 5-25-
Summary of changes:
- Updates per individual spec reviews.
Summary of changes:
- Further clarification added in spec per Munich’s answers to various questions.
- Further updates per individual spec reviews.
- Changes from Rev. 0.9 of the MSCAN12_2 spec:
- Changed the reset state of CSWAI bit to 0.
Summary of changes:
- Added RXACT flag in CANCTL0 register in bit 6 per the Project Change Request received from the Munich Design Center. This flag will provide an indication that the MSCAN is receiving a message.
- Added further clarification on low power options for Run, Wait, and Stop modes. Added description that the MSCAN clocks will shut down if MSCAN is disabled. Also added description regarding the disabling of input hysteresis in Wait & Stop modes.
- Clarified recovery from STOP or WAIT functionality. The MSCAN can wake the MCU up out of either STOP or WAIT via the wake-up interrupt if SLPAK=1.
- Added note regarding interrupt request clearing behavior--will be delayed one cycle once flag is cleared.
- Added further clarification on write conditions for CANIDAC and CANTEST registers.
- Added additional Warning for the receive & transmit error counter registers. May read an incorrect value if registers are read in any other mode other than sleep or soft reset and for MCUs with dual CPUs, may also cause a CPU fault condition to occur.
- Added additional Warning for reading the receive buffer registers. For MCUs with dual CPUs, may cause a CPU fault condition to occur if the receive buffers are read while the RXF flag is cleared.
- Corrected the RDPCAN bit description. Reduced drive is not selectable for the TxCAN and RxCAN pins if the MSCAN is enabled.
- Added further clarification on CANPORT and CANDDR reads/writes of CANP1-0 when the MSCAN is enabled.
- Enabled the pullups out of reset for the entire CAN port (PUPCANE=1 out of reset). Removed cautions regarding the need to have an external pullup on TxCAN to avoid CAN protocol violations. Added further explanations regarding the protection mechanism against violating the CAN protocol (pullups enabled and CANE write once in normal modes).
- Removed scan information in DFT section in Section 2. Added that all clocks will be stopped when MCU is in scan mode.
- Updated I/O signal list in Section 2.
- Updated module variability section in Section 2.
- Changed mscanclke signal in module variability section. Will not leave unconnected if MCU does not have an SCG module, but will use in the oscillator to enable the mscanclk.
- Added REGWRT bit to CANTEST register. Bit used to enable CPU write access to the test registers. Added bit and write descriptions. Modified RAMBO bit description.
- Updated test register read/write condition in Section 2.
- Added Port CANP pin connections table in Section 2.
- Changed minimum bit transfer rate from dc to 10KBps in Appendix A, AC Electrical Characteristics section.
- Updated/added spec tags.
Version
Number
Revision
Date
Effective
Date Author^ Description of Changes
Summary of Changes:
- Added bus activity flag for Volvo, RXFRM in CANCTL0 register in bit 7 per the Project Change Request received from the Munich Design Center. This flag will provide an indication that the MSCAN has received a valid message correctly.
- Added further clarification on how to program the CANIDMRx registers when receiving standard identifiers.
- Updated CANPORT and CANDDR read/write conditions per Architectural Definition review #3.
- Changed timer channel references from channel m to channel x to be consistent with signal name used in RTL.
- Spec tags updated per MSCAN requirements.
- Corrected write descriptions for CANCRCH/L, CANRXSHR, CANRXSHR registers in Section 2.
- Updated MSCAN clock enable module variations in Section 2.
- Corrected spelling errors.
Summary of Changes:
- In register map, changed CANRXFG (foreground receive buffers) to indicate write is unimplemented.
- Changed REGWRT bit name to ECLOAD since bit is now used to load only the error counters with test data. Also changed the write conditions for this bit. It is no longer required for SFTRES to be set to write to ECLOAD.
- Changed the implementation for loading the error counters with a test value. Updated ECLOAD per the new implementation. Also added a description in CANRXERR and CANTXERR of how to load the error counters with a desired value in test mode.
- Updated max System and MSCAN clock frequency’s per decision to design all modules to 16MHz max.
- Changed vsc_smod_t4 to vsc_smod_t2 per smod timing change request.
- Added footnote for TWUP parameter in Appendix A.
- Corrected Port CANP data out signal names in Table 2-4.
- Update module I/O list in Section 2.
Summary of Changes:
- Added clarification for RXFRM and RXACT behaviour in loop back mode.
- Corrected format for CANRXERR and CANTXERR register write descriptions in Section 2.
Summary of Changes:
- Added CAUTION to CANDDR register description. Need to wait one cycle before reading the CANPORT register after writing to the CANDDR register when DDR changed to inputs.
Summary of Changes:
- Clarified Receive/Transmit buffer read/write capability.
- Updated Table 2-5 Engineering Electrical Specs min VDD from 2.7V to 3.0V.
Version
Number
Revision
Date
Effective
Date Author^ Description of Changes
Summary of Changes:
- When Listen-Mode is active the TXEx flags in the CANTFLG register cannot be cleared and no CAN message is transmitted.
- In special test mode the RxBuffers are read/writable from the IPbus side.
Summary of Changes:
- Updated Spec.Tagging
- Reserved bits/bytes within Tx-/Rx-Buffer range are read as “x” instead of “0”
- Changed reset values for Tx-/Rx-Buffers
Summary of Changes:
- Updated Table 1-9 CPU vs. MSCAN Operating Modes
- Corrected typo in INITAK handshake flag (1.7.1.2)
- Updated wake-up note for WUPE flag (1.7.1.1)
Summary of Changes:
- Added information on the blocking mechanism for transmit buffers which are scheduled for transmission (TXEx flag cleared) (see 1.7.1.7 & 1.7.1.11).
- Added information on the read value (’x’) for unused bits in the transmit/receive buffers (see 1.7.2).
2.05 08-11-00 08-11-
Summary of Changes:
- Added 5th Rx Message Buffer to MSCAN. 2.06 20-11-00 20-11-00 - Reformated MSCAN spec form MMD-format to SRS2.
V02.
13 MAR
13 MAR
2001 - Updated according to requirements of SRSv2 supplement.
V02.
17 JUL
17 JUL
2001 - 1st offical version by Technical Publishing
V02.
10 JUL
10 JUL
- Updated according to requirements of SRSv
- Corrected footnote 1 in INITRQ description.
V02.
10 OCT
10 OCT
2001 - Replaced all references w.r.t. new family name HCS12.
V02.11 22 OCT
22 OCT
- Corrected figure title and note of CANTIER.
- Corrected local enable register names in table 4-4 ’CRG Interrupt Vectors’.
- Updated block diagram.
- Corrected section ’Description of Interrupt Operation’.
V02.
04 MAR
04 MAR
2002 - Document format updates.
V02.
22 JUL
22 JUL
- Corrected TBPR register offset.
- Corrected Table ’Message Buffer Organization’.
- Corrected SLPRQ bit description.
- Corrected MSCAN Sleep Mode description.
- Updated WUPE bit description.
- Updated Simplified State Transitions figure.
- Updated Recovery from STOP or WAIT description and CPU vs. MSCAN Modes table.
V02.
18 SEP
18 SEP
- Added Initialization/Application information.
- Replaced ’MCU’ with ’CPU’ in several places.
- Cleaned up Mode descriptions.
- General cleanup.
Version
Number
Revision
Date
Effective
Date Author^ Description of Changes
- 1.1 Overview. Section 1 Introduction
- 1.2 Features
- 2.1 Overview. Section 2 External Signal Description
- 2.2 Detailed Signal Description
- 2.2.1 RXCAN — CAN Receiver Input Pin
- 2.2.2 TXCAN — CAN Transmitter Output Pin.
- 2.3 CAN System
- 3.1 Overview. Section 3 Memory Map/Register Definition
- 3.2 Module Memory Map
- 3.3 Register Descriptions
- 3.3.1 Programmer’s Model of Control Registers
- 3.3.2 Programmer’s Model of Message Storage.
- 4.1 General. Section 4 Functional Description
- 4.2 Message Storage
- 4.2.1 Message Transmit Background
- 4.2.2 Transmit Structures
- 4.2.3 Receive Structures.
- 4.3 Identifier Acceptance Filter
- 4.3.1 Protocol Violation Protection
- 4.3.2 Clock System
- 4.4 Timer Link.
- 4.5 Modes of Operation
- 4.5.1 Normal Modes
- 4.5.2 Special Modes
- 4.5.3 Emulation Modes
- 4.5.4 Listen-Only Mode
- 4.5.5 Security Modes
- 4.6 Low Power Options
- 4.6.1 CPU Run Mode
- 4.6.2 CPU Wait Mode
- 4.6.3 CPU Stop Mode
- 4.6.4 MSCAN Sleep Mode
- 4.6.5 MSCAN Initialization Mode
- 4.6.6 MSCAN Power Down Mode.
- 4.6.7 Programmable Wake-Up Function.
- 4.7 Reset Initialization
- 4.8 General.
- 4.9 Description of Interrupt Operation
- 4.9.1 Transmit Interrupt.
- 4.9.2 Receive Interrupt
- 4.9.3 Wake-Up Interrupt
- 4.9.4 Error Interrupt.
- 4.10 Interrupt Acknowledge
- 4.11 Recovery from STOP or WAIT
- 5.1 MSCAN initialization Section 5 Initialization/Application Information
- Figure 1-1 MSCAN Block Diagram List of Figures
- Figure 2-1 The CAN System
- Figure 3-1 MSCAN Control 0 Register (CANCTL0)
- Figure 3-2 MSCAN Control 1 Register (CANCTL1)
- Figure 3-3 MSCAN Bus Timing Register 0 (CANBTR0)
- Figure 3-4 MSCAN Bus Timing Register 1 (CANBTR1)
- Figure 3-5 MSCAN Receiver Flag Register (CANRFLG)
- Figure 3-6 MSCAN Receiver Interrupt Enable Register (CANRIER)
- Figure 3-7 MSCAN Transmitter Flag Register (CANTFLG)
- Figure 3-8 MSCAN Transmitter Interrupt Enable Register (CANTIER)
- Figure 3-9 MSCAN Transmitter Message Abort Request (CANTARQ)
- Figure 3-10 MSCAN Transmitter Message Abort Control (CANTAAK)
- Figure 3-11 MSCAN Transmitter Flag Register (CANTBSEL)
- Figure 3-12 MSCAN Identifier Acceptance Control Register (CANIDAC).
- Figure 3-13 Reserved Registers
- Figure 3-14 MSCAN Receive Error Counter Register (CANRXERR)
- Figure 3-15 MSCAN Transmit Error Counter Register (CANTXERR)
- Figure 3-16 MSCAN Identifier Acceptance Registers (1st Bank)
- Figure 3-17 MSCAN Identifier Acceptance Registers (2nd Bank)
- Figure 3-18 MSCAN Identifier Mask Registers (1st Bank)
- Figure 3-19 MSCAN Identifier Mask Registers (2nd Bank).
- Figure 3-20 Receive / Transmit Message Buffer Extended Identifier
- Figure 3-21 Standard Identifier Mapping.
- Figure 3-22 Transmit Buffer Priority Register (TBPR).
- Figure 3-23 Time Stamp Register (TSRH - High Byte)
- Figure 3-24 Time Stamp Register (TSRL - Low Byte)
- Figure 4-1 User Model for Message Buffer Organization
- Figure 4-2 32-bit Maskable Identifier Acceptance Filter
- Figure 4-3 16-bit Maskable Identifier Acceptance Filters
- Figure 4-4 8-bit Maskable Identifier Acceptance Filters
- Figure 4-5 MSCAN Clocking Scheme.
- Figure 4-6 Segments within the Bit Time
- Figure 4-7 Sleep Request / Acknowledge Cycle.
- Figure 4-8 Simplified State Transitions for Entering/Leaving Sleep Mode
- Figure 4-9 Initialization Request/Acknowledge Cycle
- Table 3-1 MSCAN Register Organization List of Tables
- Table 3-2 Module Memory Map
- Table 3-3 Synchronization Jump Width
- Table 3-4 Baud Rate Prescaler
- Table 3-5 Time Segment 2 Values.
- Table 3-6 Time Segment 1 Values.
- Table 3-7 Identifier Acceptance Mode Settings
- Table 3-8 Identifier Acceptance Hit Indication
- Table 3-9 Message Buffer Organization
- Table 3-10 Data length codes
- Table 4-1 Time Segment Syntax
- Table 4-2 CAN Standard Compliant Bit Time Segment Settings
- Table 4-3 CPU vs. MSCAN Operating Modes
- Table 4-4 CRG Interrupt Vectors
Section 1 Introduction
1.1 Overview
The Motorola Scalable Controller Area Network (MSCAN) definition is based on the MSCAN
definition which is the specific implementation of the Motorola Scalable CAN concept targeted for the
Motorola MC68HC12 Microcontroller Family.
The module is a communication controller implementing the CAN 2.0 A/B protocol as defined in the
BOSCH specification dated September 1991. For users to fully understand the MSCAN specification, it
is recommended that the Bosch specification be read first to familiarize the reader with the terms and
concepts contained within this document.
The CAN protocol was primarily, but not only, designed to be used as a vehicle serial data bus, meeting
the specific requirements of this field: real-time processing, reliable operation in the EMI environment of
a vehicle, cost-effectiveness and required bandwidth.
MSCAN utilizes an advanced buffer arrangement resulting in a predictable real-time behavior and
simplifies the application software.
Figure 1-1 MSCAN Block Diagram
RXCAN
TXCAN
Receive/ Transmit Engine
Message Filtering and Buffering
Control and Status Wake-Up Interrupt Req.
Errors Interrupt Req.
Receive Interrupt Req.
Transmit Interrupt Req.
CANCLK
Bus Clock
Configuration
Oscillator Clock MUX Presc.
Tq Clk
MSCAN
Low Pass Filter
Registers Wake-Up
Section 2 External Signal Description
2.1 Overview
This section lists and describes the signals that connect off chip.
2.2 Detailed Signal Description
The MSCAN uses two external pins.
2.2.1 RXCAN — CAN Receiver Input Pin
RXCAN is the MSCAN receiver input pin.
2.2.2 TXCAN — CAN Transmitter Output Pin
TXCAN is the MSCAN transmitter output pin. The TXCAN output pin represents the logic level on the
CAN bus:
0 = Dominant state 1 = Recessive state
2.3 CAN System
A typical CAN system with MSCAN is shown in Figure 2-1. Each CAN station is connected physically
to the CAN bus lines through a transceiver chip. The transceiver is capable of driving the large current
needed for the CAN bus and has current protection against defected CAN or defected stations.
Figure 2-1 The CAN System
CAN Bus
CAN Controller (MSCAN)
Transceiver
CAN node 1 CAN node 2 CAN node n
CAN_H CAN_L
MCU
TXCAN RXCAN
