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Material Type: Notes; Professor: Khan; Class: Analog and Digital Electronics; Subject: Electrical Engineering; University: University of South Alabama; Term: Unknown 1989;
Typology: Study notes
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CMOS Inverter
Chapter 16.
p-Channel MOSFET
p
p
n
p
n
TP
p-Channel MOSFET
Cross-section of p-channel enhancement mode MOSFET
The most abundant devices on earth
Although the processing is more complicated for CMOS circuits than for NMOScircuits,
CMOS has replaced NMOS at all level of integration, in both analog
and digital applications.
¾
The basic reason of this replacement is that the power dissipation in CMOSlogic circuits is much less than in NMOS circuits.
Full rail-to-rail swing
high noise margins
z
Logic levels not dependent upon the relative device sizestransistors can be minimum size
ratio less
Always a path to
V
DD
or GND in steady state
low
output impedance (output resistance in
k Ω
range)
large fan-out.
Extremely high input resistance (gate of MOS transistor
is near perfect insulator)
nearly zero steady-state
input current
No direct path steady
no static power dissipation
Propagation delay function of load capacitance and resistance of transistors
¾
In the fabrication process, a separate
p-well
region is
formed within the starting n
substrate.
¾
The n
c hannel MOSFET is fabricated in the p
w
ell region
and p
c
hannel MOSFET is fabricated in the n
s ubstrate.
DD
n
Out
In
DD
p
Out
DD
In
DD
OL OH
Voltage Transfer Curve
DN (A)
out
X
10
-
V
in
= 1.0V
V
in
= 1.5V
V
in
= 2.0V
V
in
= 2.5V
0.25um, W/L
n
= 1.5, W/L
p
= 4.5, V
DD
= 2.5V, V
Tn
= 0.4V, V
Tp
= -0.4V
V
in
= 0V
V
in
= 0.5V
V
in
= 1.0V
V
in
= 1.5V
V
in
= 0.5V
V
in
= 2.0V
V
in
=1.0V
V
in
=0V
V
in
=0.5V
V
in
=2.5V
V
in
=2.0V
V
in
=1.5V
DP (A)
NMOS off
PMOS in non sat
NMOS in satPMOS in non
sat
NMOS in satPMOS in sat
NMOS in non
sat
PMOS in sat
NMOS in nonsat PMOS off
v
SDP
is small v
I^
and
v O
relationship as long as
NMOS: saturation, PMOS: nonsaturation
from below graph v
OPt
or
from above graph v
ONt
v
It
NMOS: nonsaturationPMOS: off
NMOS: nonsaturationPMOS: saturation
NMOS: saturationPMOS: saturation
NMOS: saturationPMOS: nonsaturation
NMOS: offPMOS: nonsaturation
CMOS Inverter Design Consideration
The CMOS inverter usually design to have,
This can achieved if
width of the PMOS
is made two or
three times than that of the NMOS device.
9
This is very important in order to provide a symmetrical transition
results in wide noise margin.
But
(because
μ
N
μ
P
(1) (2)
V
V
=
=
L W
k
L W
k
'
'
P
N
k
k
¾
How equation (2) can be satisfied?
NMOS: nonsaturationPMOS: off
NMOS: nonsaturationPMOS: saturation
NMOS: saturationPMOS: saturation
NMOS: saturationPMOS: nonsaturation
NMOS: offPMOS: nonsaturation
Symmetrical Properties of the CMOS Inverter
v
OPt v
ONt
DD 2
It
V
V
=
Example 16.
p
(a)
i
Transition points
V
OPt V
ONt
ii
v
It
v
OPt
v
ONt
k
n
N
'
Example 16.
p
(b)
i
ii
Transition points
V
OPt V
ONt
k
P
P
'
Increase
W
of PMOS
¼
k
P
increases
¼
V
It
moves to right
DD
DD
V
In
V
Out
k
p
k
n
k
p
k
n
k
p
k
n
CMOS Inverter
V
Increase
W
of NMOS
¼
k
N
increases
¼
V
It
moves to left
P
N
P
N
DD
It
W
W
k
k
V
V
for
≈
=
→
=
, 2
V
It
Inverter threshold
It
DD
Rise and fall delays unequal
Noise margins not equal
Want a faster delay for one type of transition (rise/fall)
¾
Remove noise from input signal: increase one noise marginat expense of the other
CMOS Inverter
V
Effects of
V
It
adjustment
When NMOS transistor is biased in the saturation region
The current in the inverter is controlled by
v
GSN
and the PMOS
v
SDP
adjusts
such that
i DP
i
DN
As long as NMOS transistor is biased in the saturation region thesquare root of the inverter current is linear function of the input voltage.
When PMOS transistor is biased in the saturation region
The current in the inverter is controlled by
v
SGP
and the NMOS
v
DSN
adjusts
such that
i DP
i DN
As long as PMOS transistor is biased in the saturation region thesquare root of the inverter current is linear function of the input voltage.
NMOS: saturationPMOS: saturation
NMOS: offPMOS: nonsaturation
NMOS: saturationPMOS: nonsaturation
NMOS: nonsaturationPMOS: off
NMOS: nonsaturationPMOS: saturation
Problem 16.
p
(a) (b)
Power Dissipation
¾
There is
no power dissipation in the CMOS inverter
when the output is either at logic 0 or 1. However, during switching
of the CMOS inverter from low logic 0 to logic 1,
current flows and power is dissipated.
¾
Usually CMOS inverter and logic circuit are used to driveother MOS devices by connecting a capacitor across theoutput of a CMOS inverter. This
capacitor
must be charged
and discharged during the switching cycle.
Triode Region
NMOS Transistor Capacitances
ox
= Gate-Channel capacitance per unit area(
F/m
2
GC
= Total gate channel capacitance
GS
= Gate-Source capacitance
GD
= Gate-Drain capacitance
GSO
and
GDO
= overlap capacitances (
F/m
Saturation Region
NMOS Transistor Capacitances
Drain is no longer connected to channel.
Cutoff Region
NMOS Transistor Capacitances
Conducting channel region is completely gone. C
GB
= Gate-Bulk capacitance
GBO
= Gate-Bulk capacitance per unit width.
Case II: when the input is high and out put is low:
During switching all the energy stored in the loadcapacitor is dissipated in the NMOS device becauseNMOS is conducting and PMOS is in cutoff mode.The energy dissipated in the NMOS inverter;The total energy dissipated during one switching cycle;The power dissipated in terms frequency;
2
12
DD L
N
V C
E
=
2
2
2
12
12
DD L
DD L
DD L
N
P
T
V C
V C V C E E E
=
=
=
(^2) DD
L
T
T
T
This implied that the
power dissipation
in the
CMOS inverter is directly proportional to switchingfrequency and
V
DD
2
¾
Does not (directly) depend on device sizes
¾
Does not depend on switching delay
¾
Applies to general CMOS gate in which:
Switched capacitances are lumped into
L
Output swings from GND to
DD
Input signal approximated as step function
Gate switches with frequency
f
DD
L
dyn
2
Formula for dynamic power
¾
Short
c ircuit current flows from
V
DD
to GND when both
transistors are on saturation mode. V
DD
DD
max
depends on saturation current of devices
tot
leak
f
r
tot
stat
sc
dyn
tot
max
DD
L
dyn
2
Power Reduction
Lower the voltage
!!
Quadratic effect on dynamic power
¾
Reduce capacitance
!!
Short interconnect lengths
Drive small gate load (small gates, small fan-out)
¾
Reduce frequency
!!
Lower clock frequency
Lower signal activity
Fast rise/fall times on input signal
¾
Reduce input capacitance
¾
Insert small buffers to “clean up” slow inputsignals before sending to large gate
Small transistors (leakage proportional towidth)
¾
Lower voltage
Power Reduction
