Modern digital electronics by r p jain solution manual, Study notes of Advanced Computer Architecture

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R P Jain

Solution Manual

for

Modern Digital Electronics

Third Edition

CHAPTER 1

1.1 (a) Analog. The output of a pressure gauge is proportional to the pressure being measured and can assume any value in the given range. (b) Digital. An electric pulse is produced for every person entering the exhibi- tion using a photoelectric device. These pulses are counted using a digital circuit. (c) Analog. The reading of the thermometer is proportional to the temperature being measured and can assume any value in the given range. (d) Digital. Inputs are given with the help of switches, which are converted into digital signals 1 and 0 corresponding to the switch in the ON or OFF position. These signals are processed using digital circuits and the results are displayed using digital display devices. (e) Analog. It receives modulated signals which are analog in nature. These signals are processed by analog circuits and the output is again in the analog form. (f) Digital. It has only two possible positions (states), ON and OFF. (g) Digital. An electric pulse is produced for every vote cast by pressing of switch of a candidate. The pulses thus produced for each candidate are counted separately and also the total number of votes polled are counted. 1.2 (a)

(i) S 1 S 2 Bulb (ii) S 1 S 2 Bulb OFF OFF OFF OFF OFF OFF OFF ON OFF OFF ON ON ON OFF OFF ON OFF ON ON ON ON ON ON ON

(iii) S Bulb (iv) S 1 S 2 Bulb OFF ON OFF OFF OFF ON OFF OFF ON ON ON OFF ON ON ON OFF (b)

(i) S 1 S 2 Bulb (ii) S 1 S 2 Bulb 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 1 0 1 1 1 1 1 1 1

(iii) S Bulb (iv) S 1 S 2 Bulb 0 1 0 0 0 1 0 0 1 1 1 0 1 1 1 0

(c) (i) AND (ii) OR (iii) NOT (iv) EX-OR

1.5 For Fig. 1.

(a) A Y (b) A B (^) AB Y 0 1 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 1 0 1

(c) A B A B Y 0 0 1 1 0 0 1 1 0 1 1 0 0 1 1 1 1 0 0 1

For Fig. 1. (a) A Y (b) A B (^) A + B Y 0 1 0 0 1 0 1 0 0 1 0 1 1 0 0 1 1 1 0 1

(c) A B (^) A B Y 0 0 1 1 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 1

1.6 (a) NAND, NOR (b) AND (c) NAND (d) OR

1.7 (a)

Inputs A B^ A B Output A B Y 0 0 0 0 0 0 1 0 1 1 1 0 1 0 1 1 1 0 0 0

(b) EX–OR (c) A

B

Y

(d) Y = AB^ + A B \ (^) Y = AB + A B

= AB ⋅ AB

Y =^ Y^ =^ AB^ ⋅ AB

= Y 1 ⋅ Y 2

where, Y 1 = AB and Y 2 = AB

A

B

Y

Y 1

Y 2

1.8 For simplicity, we shall consider 2-input gates, but the results are equally valid for any number of inputs. In the positive logic system, the higher of the two voltages is designated as 1 and the lower voltage as 0. On the other hand in the negative logic system, the lower of the two voltage is designated as 1 and the higher voltage as 0. Therefore, if 1s and 0s are interchanged, the logic system will change from positive to negative and vice-versa. (a) In the truth table of positive logic AND gate replace all zeros by ones and all ones by zeros. The resulting truth table is same as that of the OR gate. Similarly, if all ones and zeros are interchanged in the truth table of the OR gate, the resulting truth table will be same as that of the AND gate. (b) Repeat part (a) for NAND and NOR gates.

1.9 (a) A + A B + A B = ( A + A B ) + A B

= A (1 + B ) + A B = A ◊ 1 + A B = A + A B = ( A + A ) ( A + B ) = A + B (b) AB + A B + A B = ( A + A ) B + A B = B + A B = ( B + A ) ( B + B ) = A + B (c) (^) A BC + A B C + ABC + ABC = A BC + A B C + AB ( C + C ) = A BC + A B C + AB = A BC + A ( B + (^) B C ) = (^) A BC + A ( B + (^) B ) ( B + C )

(b) The realization of LHS requires two inverters, three 2-input AND gates and one 3-input OR gate, whereas the realization of RHS requires only one inverter and one 2-input OR gate.

A

B

A B

(c) The realization of LHS requires three inverters, four 3-input AND gates and one 4-input OR gate, whereas the realization of RHS requires only three 2-input AND gates and one 3-input OR gate.

A

B

C

(i)

A

B

C

(ii)

1.12 (a) AB + CD (^) = AB + CD = AB ⋅ CD

(i) (ii)

(b) ( A + B ) ( C + D ) = ( A^ + B^ ) ⋅ ( C^ + D )

= ( A + B ) + ( C + D ) (i) The left hand side of (a) can be realized by using two 2-input AND gates followed by one 2-input OR gate, while the right hand side is realizable by two 2-input NAND gates followed by another 2-input NAND gate. Hence an AND-OR configuration is equivalent to a NAND- NAND configuration. (ii) The left hand side of (b) is realizable by two 2-input OR gates followed by a 2-input AND gate, while the right hand side is realizable by two 2-input NOR gates followed by another 2-input NOR gate. Hence an OR-AND configuration is equivalent to a NOR-NOR configuration.

Y

A B

C D

Y

A B

C D (i) (ii)

A B

C D

A B

C D (i) (ii)

Y Y

1.14 (a) Since A ◊ B = B ◊ A Therefore, the AND operation is commutative. If A ◊ ( B ◊ C ) = ( A ◊ B ) ◊ C , then the AND operation is associative. This can be proved by making truth table as given below:

A B C ( A ◊ B ) ◊ C A ◊ ( B ◊ C ) 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1

(a)

(b)

A B

C

D

A ≈ B

A ≈ B ≈ C

A ≈ B ≈ C ≈ D

Y

or

A B

C D

A ≈ B

C ≈ D

Y A ≈ B ≈ C ≈ D

Fig. 1.

In the same way we can try higher number of ones. It is obvious from the above discussion that Z = 1, if an odd number of variables are 1 and Z = 0 if an even number of variables are 1. 1.18 Since a logical variable can assume one of the two values (0 or 1) the number of possible combinations is 2 N. Take an N -bit binary number b (^) N –1 b (^) N –2... b 2 b 1 b 0 and write all combina- tions from 00... 000 to 11... 111 in normal binary ascending order. 1.19 (a) 7402 is a quad 2-input NOR gate. This means there are four identical 2-input NOR gates. Each gate requires three pins, two for inputs and one for output. Therefore, the four gates requires 3 ¥ 4 = 12 pins. Two pins are required for the power supply ( V (^) CC and GND). Hence it is a 14-pin IC. (b) 7404 is a hex inverter. The number of pins = 2 ¥ 6 + 2 = 14. (c) 7408 is a quad 2-input AND gate. The number of pins = 3 ¥ 4 + 2 = 14. (d) 7410 is a triple 3-input NAND gate. The number of pins = 4 ¥ 3 + 2 = 14. (e) 7411 is a triple 3-input AND gate. The number of pins = 4 ¥ 3 + 2 = 14. (f) 7420 is a dual 4-input NAND gate. The number of pins = 5 ¥ 2 + 2 = 12. Since 12-pin IC package is not used, therefore, it is packaged as 14-pin IC. Two pins are left free (NC). (g) 7427 is a triple 3-input NOR gate. The number of pins = 4 ¥ 3 + 2 = 14. (h) 7432 is a quad 2-input OR gate. The number of pins = 3 ¥ 4 + 2 = 14.

(i) 7486 is a quad EX-OR gate. The number of pins = 3 ¥ 4 + 2 = 14. 1.20 (a) (i) 7408 and 7432 (ii) 7400 (b) (i) 7432 and 7408 (ii) 7402 1.21 Logic Circuit A 0.4 V = 0 2 V = 1 Logic Circuit B –0.75 V = 1 –1.55 V = 0

Inputs Output AND OR NAND NOR A B C Y 1 Y 2 Y 3 Y 4 0 0 0 0 0 1 1 0 0 1 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 0 1 0 0 0 1 1 0 1 0 1 0 1 1 0 1 1 0 0 1 1 0 1 1 1 1 1 0 0

1.23 Yes.

A B C

Logic 1

Y or^ Y

A B C

(a)

Y

A B C

or

A B C

Y

Logic 0

(b)

A B C

A B C

Y (^) or Y

Logic 1

(c)

A B C

A B C

Y (^) or Y

Logic 0

(d)

1.28 (a) A ≈ B = A B + A B

A ≈ B = (^) AB + A B = A B + A B = A ≈ B (b) (^) A ⊕ B = AB + AB A ≈ B = (^) AB + A B = AB + AB A ≈^ B^ =^ AB + A B = AB + AB (c) B ≈ ( B ≈ AC ) = B ≈ B ≈ AC = 0 ≈ AC = AC

CHAPTER 2

(a) 111001 = 1 ¥ 25 + 1 ¥ 24 + 1 ¥ 23 + 0 ¥ 22 + 0 ¥ 21 + 1 ¥ 20 = 32 + 16 + 8 + 0 + 0 + 1 = (57) 10 (b) 101001 = 1 ¥ 25 + 0 ¥ 24 + 1 ¥ 23 + 0 ¥ 22 + 0 ¥ 21 + 1 ¥ 20 = 32 + 0 + 8 + 0 + 0 + 1 = (41) 10 (c) 11111110 = 1 ¥ 27 + 1 ¥ 26 + 1 ¥ 25 + 1 ¥ 24 + 1 ¥ 23 + 1 ¥ 22

• 1 ¥ 2 1 + 0 ¥ 20 = 128 + 64 + 32 + 16 + 8 + 4 + 2 + 0 = (254) (^10) (d) 1100100 = 64 + 32 + 0 + 0 + 4 + 0 + 0 = (100) (^10) (e) 1101.0011 = 1 ¥ 23 + 1 ¥ 22 + 0 ¥ 21 + 1 ¥ 20 + 0 ¥ 2 –1^ + 0 ¥ 2 –
• 1 ¥ 2 –3^ + 1 ¥ 2 – = 8 + 4 + 0 + 1 + 0 + 0 + 0.125 + 0. = (13.1875) (^10) (f) 1010.1010 = 8 + 2 + 0.5 + 0. = (10.625) 10 (g) 0.11100 = 0.5 + 0.25 + 0. = (0.875) 10 2.2 (a) Quotient Remainder

37 2

Thus (37) 10 = (100101) 2 Similarly, (b) (255) 10 = (11111111) 2 (c) (15) 10 = (1111) (^2)

(b) 01100 fi 01100 –00011 + 11101 (2’s complement) 101001 = + 9 ≠ Ignore (c) 0011.1001 fi 0011. –0001.1110 +1110.0010 (2’s complement) 10001.1011 = + 1. ≠ Ignore

2.5 (a) Quotient Remainder

375 8

Therefore, (375) 10 = (567) 8 = (101110111) (^2) (b) Quotient Remainder 249 8 31 1 31 8 3 7 3 8

Therefore, (249) 10 = (371)8 = (011111001) (^2) (c) Integer part: (27) 10 = (33) 8 = (011011) 2 Fractional part: 0. ¥ 8

Ø 1 Thus (0.125) 10 = (0.1) 8 = (0.001) (^2) Therefore, (27.125) 10 = (33.1) 8 = (011011.001) (^2)

2.6 (a) 11 011 100.101 010 = (334.52) (^8)

(334.52) 8 = 3 ¥ 82 + 3 ¥ 81 + 4 ¥ 80 + 5 ¥ 8 –1^ + 2 ¥ 8 – = (220.65625) (^10) (b) 01 010 011.010 101 = (123.25) 8 = (83.328125) (^10) (c) 10 110 011 = (263) 8 = (179) (^10)

2.7 (a) Quotient Remainder

375 16

Therefore, (375) 10 = (177) 16 (or 177H) = (0001 0111 0111) (^2) (b) Quotient Remainder 249 16 15 9 15 16

F 9

Therefore, (249) 10 = (F9) 16 (or F9H) = (1111 1001) (^2) (c) Integer part: Quotient Remainder 27 16

1 B

Thus (27) 10 = 1BH Fractional part:

¥ 16

Ø 2 \ (0.125) 10 = 0.2H \ (27.125) 10 = (1B.2) 16 = 1B.2H = (00011011.0010) 2 2.8 (a) 1101 1100.1010 10 = (DC.A8) 16 (DC.A8) 16 = 13 ¥ 161 + 11 ¥ 16 0 + 10 ¥ 16 –1^ + 8 ¥ 16 – = (220.65625) 10 (b) 0101 0011.0101 01 = (53.54) 16 = (83.328125) 10 (c) 1011 0011 = (B3) 16 = (179) (^10) 2.9 For each decimal digit write its natural BCD code (a) 46 = 0100 0110 (BCD) (b) 327.89 = 0011 0010 0111.1000 1001 (BCD) (c) 20.305 = 00100000.0011 0000 0101 (BCD) 2.10 For each decimal digit write its 4-bit Excess-3 code. (a) 46 = 0111 1001 (Excess-3) (b) 327.89 = 0110 0101 1010.1011 1100 (Excess-3) (c) 20.305 = 0101 0011.0110 0011 1000 (Excess-3)

In a similar way parity bit can be attached to every character. (b) Repeat part (a) for EBCDIC code. 2.15 (a) Attach 0 or 1 as MSB to make the number of ones odd. For example, 8-bit ASCII code for R with odd parity is 01010010 (b) Repeat part (a) for EBCDIC code. 2.16 (a) Since, 2^5 = 32 and 2 6 = 64, therefore, the minimum number of bits required to encode 56 elements of information is 6. (b) 2 7 < 130 < 2 8 Therefore, 8 bits are required to encode 130 elements of information. 2.17 In the 8 bit ASCII code with the parity bit, if binary to hexadecimal conversion is used, the resulting format will be hexadecimal. For example, R = 11010010 = D 2 H and l = 00101110 = 2EH for even parity and R = 01010010 = 52H and l = 10101110 = AEH for odd parity. 2.18 Consider the following examples: (i) 7 0111 fi 0111 –3 –0011 + 1100 (1’s complement) 4 10011 1 End-Around Carry (EAC) 0100 = 4 (ii) 3 0011 fi 0011 –7 – 0111 + 1000 (1’s complement) –4 1011 = –4 in 1’s complement form From the above examples the rules of subtraction can be summarized as: (a) Add ones complement of the subtrahend to the minuend. (b) If a carry is produced, add end-around carry (EAC) (c) If the MSB of the sum is 0, the result is positive (d) If the MSB of the sum is 1, the result is negative and it is in one’s complement format. 2.19 100 ¥ 20 ¥ 8 bits. 2.20 132 ¥ 7 bits. 2.21 Let us consider the BCD code for 9 and find out its Hamming code for error correction. Hamming Code Decimal Position Æ 1 2 3 4 5 6 7 digit p 1 p 2 n 1 p 3 n 2 n 3 n 4 9 BCD : : 1 : 0 0 1 : : : : : : : odd parity for : : : : : : : 1,3,5,7 requires p 1 = 1 1 : 1 : 0 0 1 odd parity for 2,3,6,7 : : : : : : : requires p 2 = 1 1 1 1 : 0 0 1 odd parity for 4,5,6,7 : : : : : : : requires p 3 = 1 1 1 1 0 0 0 1

Therefore, Hamming code for decimal digit 9 is 1 1 1 0 0 0 1. Similarly, Hamming code is determined for each BCD digit and the complete se- quence is given below. Hamming code Decimal Position Æ 1 2 3 4 5 6 7 digit p 1 p 2 n 1 p 3 n 2 n 3 n 4 0 1 1 0 1 0 0 0 1 0 0 0 0 0 0 1 2 1 0 0 0 0 1 0 3 0 1 0 1 0 1 1 4 0 1 0 0 1 0 0 5 1 0 0 1 1 0 1 6 0 0 0 1 1 1 0 7 1 1 0 0 1 1 1 8 0 0 1 1 0 0 0 9 1 1 1 0 0 0 1