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ECE 2030
Section F
Quiz II
March 1
st
4:35 pm 5:55 pm
- The Georgia Tech Honor Code governs this examination.
- There are 9 questions and 14 pages including two blank worksheets. Make sure you have all of them.
- Please write/draw legibly. Use the work sheets for generating the solutions before providing the final answer.
- State any assumptions you feel you have to make or ask for clarification
- Keep in mind it is difficult to give partial credit without written material. Please make sure you document any partial solutions. 6. The points are shown next to each problem. Plan your work!
- The exam is 80 minutes.
Problem Max Points Graded 1 20 2 10 3 15 4 10 5 10 6 10 7 10 8 5 9 5 Total 100
Student Name: __________________________________
Student Number: ________________________________
- ( 20pts ) Consider the following Boolean expression to be minimized.
F = ABC + BCD + A D
a. Fill in the following K-map with entries corresponding to the minterms and maxterms. Identify all the 0’s prime implicants and denote which of these are essential.
b. From the K-map above write the simplified POS form of the expression F.
AB
CD Prime Implicants Essential?
- ( 10 pts ) Implement the two input XNOR function using a decoder and gates.
- ( 15 pts ) You are to design a system I/O interface using combinational building blocks. The inputs are the following four signals.
A – power failure indicator B – disk requires service C – network interface requires service D – keyboard requires service
There is only one interrupt signal connecting this interface unit to the CPU. When any of the preceding signals are asserted (logic 1) the interface is enabled and the highest priority signal must be routed to the CPU as shown in the figure below. Using the inputs A, B, C, and D you will implement the logic in each of the three boxes shown in the interface below including connection of the inputs.
a. Show the gate level implementation of the Enable generation circuit.
Multiplexor
control
Enable generate logic
A
B
C
D
To CPU F
c. Design an implement in basic gates the controller that correctly sets the multiplexor if one or more input signals (A,B,C, or D) are asserted. You may use any design technique you prefer. Assume priority in the order A>B>C>D.
- ( 5 pts ) Using combinational building blocks build a circuit that satisfies the following truth table. For example, when C0 = 0 and C1 = 1, input B is connected to output E.
C1 C0 Connection 0 0 A Æ E 0 1 B Æ E 1 0 C Æ G 1 1 A Æ F
A
B
C
E
F
G
- ( 5 pts ) Implement the following expression in the PLA shown by identifying the connections which should be made with an X.
F = AB + BC + AC
0 or 1?: ___
0 or 1?: ___
A B C
- ( 10 pts ) Show the design of an 8 word ROM, where each word is comprised of 8 bits. The ROM stores the ASCII encoding of “ECE 2030”. Ignore the quotation marks. The sequence has 8 characters (including the blank space). Letter E is stored in location 0. The number 0 is stored in location 7.
