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ECE 491 – Senior Design 1
Laboratory 6 – Manchester Code Transmitter
Revised October 12, 2007
Goals
• To develop an FPGA design of a circuit that transmits data using the Manchester
Code.
• To gain additional skill designing and debugging complex digital circuits using
Verilog and FPGAs.
Background
The Manchester Code transmits data serially while guaranteeing that each transmitted bit
contains either a rising or falling transmission in the center of the bit transmission period
(“cell”). Figure 1 shows a common variation of the Manchester code, in which a “1”
value is transmitted with a logic high in the first half of a cell and a logic low in the
second half. A “0” value is transmitted with a logic low in the first half of the cell and a
logic high in the second half. A third “idle” value is sometimes used when a transmitter
has no data to transmit; this makes it possible for multiple transmitters to use a shared
medium like the original Ethernet. In Figure 1, an “idle value” is transmitted as a logic
high in both halves of the cell. The fourth possibility (a logic low in both halves of the
cell) should not occur and is treated as an error.
Figure 1 – Manchester Code Bit Values
The presence of a bit transition in each cell means that a receiver circuit can re-
synchronize on each successive bit transition. This allows the transmission of a frame
(i.e., a long string of bits). In contrast, asynchronous serial transmission schemes using a
START and STOP bit can only be used to transmit short frames of data (e.g. 8 bits)
because they only synchronize on the falling transition of the START bit.
Manchester transmitters usually begin a frame with a preamble that allows clock
recovery circuits to synchronize to a starting transmission. The preamble is followed by
a Start Frame Delimiter (SFD) which signals the beginning of actual data. In IEEE 802.3
Ethernet, the preamble is a 56-bit sequence of alternating 1’s and 0’s followed by an 8-bit
SFD that transmits (LSB first) the value 11010101 (i.e., a sequence of alternating 1 and 0
values ending with two adajacent 1 values). Data is then transmitted bit-by-bit until the
end of the frame is reached and the transmitter returns to the idle state. Figure 2
illustrates this process.
