






Study with the several resources on Docsity
Earn points by helping other students or get them with a premium plan
Prepare for your exams
Study with the several resources on Docsity
Earn points to download
Earn points by helping other students or get them with a premium plan
Community
Ask the community for help and clear up your study doubts
Discover the best universities in your country according to Docsity users
Free resources
Download our free guides on studying techniques, anxiety management strategies, and thesis advice from Docsity tutors
These are the Laboratory of Digital Logic which includes Implementation, Altera Cyclone, Subfunction, Inputs to Outputs, Multiplexers and Pass Transistors, Interconnections, Maximum Expected, Two Circuits, Flip Flop etc. Key important points are: Logic Gate Parameters, Voltage Transfer Characteristic, Operating Points, Gate Representing, Noise Margins, Propagation Delay, Oscilloscope, Subsequent Experiments, Basic Terminology, Noise Margins
Typology: Lecture notes
1 / 12
This page cannot be seen from the preview
Don't miss anything!
In this experiment, you will become familiar with the terminal characteristics and parameters for digital logic gates viewed as electronic circuits. After performing this experiment, you should be able to use a mixed signal oscilloscope to:
IMPORTANT NOTICE: If you have this available before your first lab, please study this prelab material before going to lab. You will still be able to do the lab based a brief presentation by your lab instructor even if you are unable to study ahead. In this case, it is important that you study the prelab material before doing the laboratory report.
This experiment requires a number of concepts, some of which may be new to you. Section 2-8 of Mano and Kime [1] covers the basic terminology. Concepts covered or reviewed here are: 1) voltage transfer characteristics, 2) operating points, 3) noise margins, and 4) propagation delay.
The static voltage transfer characteristic of a logic gate is simply a plot of the gate output voltage VOUT versus the gate input voltage VIN. We can mathematically describe the transfer characteristic as VOUT = f(VIN). We use the word static to describe the transfer characteristic because it represents behavior in response to slowly changing signals so that dynamic effects such as the delaying of the signal from gate input to gate output are avoided in measurements.
Figure 1-1(a) shows an ideal static transfer characteristic for an inverter with input VIN, output VOUT and power supply voltage, VCC = 5.0 V. What can we learn from a static transfer characteristic that is useful in characterizing gate operation? In order to answer this question, we need to define some terminology.
First, we will consider the operating points for the inverter. These points correspond to the HIGH and LOW values on the outputs of the inverter. Since the output voltage depends on the input voltage, to find the value of the HIGH operating point for an inverter output, the value of the LOW operating point for the same inverter needs to be applied to its input. Likewise, to find the value of the LOW operating point, the value of the HIGH operating point needs to be applied. This requires that we know the values we are trying to determine! By analytically using feedback, we can combine the transfer characteristics of two identical inverters to achieve this dependency relationship.
Figure 1-1 Transfer Characteristic and Operating Points
This is done by connecting two inverters in a loop as shown in Figure 1-1(b). For the two inverters, we note that VIN2 = VOUT1 and VIN1 = VOUT2. Since both of the inverters have the same transfer characteristic, we take the transfer characteristic of inverter 2 and mirror it about the VOUT = VIN line so that its VIN axis lies coincident with the VOUT axis of the transfer characteristic for inverter 1 as shown in Fig. 1-1(b); then the VIN axis of gate 1 also coincides with the VOUT axis of gate 2. By this mirroring operation, the relationships given in Fig. 1-1(b) are satisfied on the axes of the plot. Because of the voltage equalities, the only points where both static transfer characteristics can be satisfied on this plot is where they intersect. These intersection points are (VIN1 = 0.15 V, VOUT1= 4.05 V), (VIN1 = 1.50 V, VOUT1 = 1.50 V), and (VIN1 = 4.05 V, VOUT1 = 0.15 V); these operating points are marked with OP. A small change in VIN from 1.5 V will cause departure from the (VIN1 = 1.5 V, VOUT1 = 1.5 V) point toward one of the other two points. Thus, this point is unstable , will not persist, and is of little interest. Small departures from the other two operating points, however, are reversible and with the appropriate change in VIN1 will result in a return to those points. These are stable operating points for the inverters. They define the voltage values that correspond to HIGH and LOW on inputs and outputs of this particular inverter. Since we are using positive logic , HIGH corresponds to 1 and LOW corresponds to 0. Thus for the given inverter, the voltage values for 0 and 1 are 0.15 V and 4.05 V, respectively. For VOUT, the LOW value is V output LOW , denoted VOL , and the HIGH value, V output HIGH , denoted VOH.
So, for this inverter, VOL is 0.15 V and VOH is 4.05 V. Finally, since the LOW value on the input produces a HIGH value on the output and vice-versa, an inversion of the voltage values has occurred. For either positive or negative logic, the inverter is also often called a NOT gate since it negates the input value to produce the output value. Note that if you actually connected two identical gates in a loop, you would get only an operating point, not the transfer characteristics. In the lab, we will generate the equivalent of Fig. 1-1(b) for two inverter types.
Next, we define the concept of noise margins; our approach is that used in Kang and Leblebici [2]. Noise is assumed to be an effective voltage on one or more inputs to a gate that is added to or subtracted from the voltage normally present. The normal voltage is a stable operating point voltage. Examples of sources of noise are fluctuations in the power supply voltage VCC, noise generated by other digital circuits changing values rapidly, or external electromagnetic radiation. Intuitively, noise margins represent the amount of effective noise voltage that can be tolerated on an input without seriously disturbing the gate output.
Figure 1-3 Gate Delay Parameter Definitions
Here we consider two primary gate delay parameters. In order to define these parameters, we will use an inverter as an example. We will assume that a pulse is applied to the inverter input VIN as shown in Fig. 1-3. The response to this pulse on the output of the inverter is VOUT, also shown in Fig. 1-3. The two parameters are the high-to-low propagation time , tPHL and the low-to-high propagation time , tPLH. We make both of these timing parameter measurements at the 50% level on the waveforms for VIN and VOUT. Formally, the 50% level is defined as the voltage 0.5( VOH – VOL ) + VOL. tPHL is the time measured from this voltage on the rising input waveform to the same voltage on the falling output waveform. tPLH is the time measured from this voltage on the falling input waveform to the same voltage on the rising output waveform. Note that the subscripts on these parameters refer to the direction of change on the output waveform. These two gate delay times are defined graphically on the waveforms in Fig. 1-3. In addition, we define a secondary parameter, the worst case propagation delay, tPD = Maximum ( tPHL , tPLH ). It should be noted that the 50% level for measuring delay is not universally used. For example, some manufacturers use 1.3V as the level for delay measurement for Low Power Schottky Transistor- Transistor Logic (LSTTL). Also, tPD does not universally represent the maximum propagation delay for a single gate. Some text authors use tPD to represent the average of tPHL and tPLH ; we will call this tPD(average). Returning to tPD for the case of many inverters of the same type, we are taking the worst case (maximum) values that can possibly occur for each of tPHL and tPLH and then taking the maximum of these two values. The end result, tPD , is the longest delay that can ever occur for a signal change propagating from an input of a gate to the output of the gate, regardless of the direction of the signal changes. These same parameters can also be defined from a given input to a given output of more complex integrated circuits or parts thereof.
There is no prelab write-up for this lab, but you are expected to thoroughly study the prelab material before or after the lab.
ON REPORTS: All lab results and all answers to questions or discussion are to appear in the lab reports of individual students. All tangible lab results are to be identical; when a printout of results is specified, a copy should be made for each team member. All answers to questions or discussion are to be the work of individual students, not the lab team. Evidence of collaboration on these aspects of a report within or between teams will be noted and is subject to University disciplinary action.
In this experiment, you will find the voltage transfer characteristics and parameters for two device in the High-speed Complementary Metal Oxide Semiconductor (HCMOS) logic family. In addition, you will verify the function of an HCMOS 3-input NOR gate.
In addition to the equipment already on the lab bench, your instructor will have you check out a plastic tray containing:
WARNING – LAB EQUIPMENT HANDLING: Much of the lab equipment is small and delicate. In particular, this applies to the FPGA boards, scopes, scope probes, and logic analyzer probes. So please be careful and handle the equipment with a light and careful touch and do not use the scope probes with the grabbers removed. Perform wiring on the board ONLY with the power and other cables disconnected!
WARNING – GND CONNECTIONS: Be very careful not to connect a ground clip or ground lead from the oscilloscope to VCC instead of GND! This can result in a short that causes the lead to get hot or to melt!
CAUTION – USE OF AUTOSCALE: Although AUTOSCALE may be very useful for analog measurements, it often does not set things up well for accurate digital measurements. As a consequence, we usually do NOT use it. If you accidentally use AUTOSCALE and lose your settings, you can recover them by pressing Setup and Undo Autoscale.
Objective: To find the transfer characteristic and static noise margins for a 74HC14 HCMOS Schmitt-trigger inverter.
Figure 1-6 Setup for Finding Propagation Delay
5a. Use the measured tPHL and tPLH to find both tPD and tPD(average). 5b. Compare tPD and tPD(average) with the respective worst case(maximum) value, 19 ns, and typical value, 11 ns, as listed in the datasheet for the 74HC04 [3]. Explain the likely reason(s) for any differences.
Figure 1-7 Setup for Determination of Logic Function
Return the scope to its normal operating mode, erase the contents of Mem1 and turn off channels A1 and A2.
Push D0 – D15 to activate the digital channels of the scope. Then turn ON channels D0 – D7.
Use the Entry or Select knob to select each of D4 through D7 and turn them off.
Push Labels/Threshold and select the Threshold Menu. Set the Threshold to TTL.
Press Previous Menu ‡ Define Labels.
Turn Select to select bit_03.
Set the Position to the far left.
Use Entry to select characters and Copy to enter them to spell Y.
Press Assign Label to label bit_03 as Y.
Press Label -> ON.
Press Previous Menu and Display to return to display mode.
Press Main/Delayed and set the Time Ref to Left.
Connect board power.