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MOS Digital Circuits
Chapter 16
• In the late 70s as the era of LSI and VLSI
began, NMOS became the fabricationtechnology choice.
• Later the design flexibility and other
advantages of the CMOS were realized,CMOS technology then replaced NMOS at alllevel of integration.
• The small transistor size and low power
dissipation of CMOS circuits, demonstrationprincipal advantages of CMOS over NMOScircuits.
NMOS Inverter
• For any IC technology used in digital
circuit design, the basic circuit elementis the logic inverter.
• Once the operation and
characterization of an inverter circuitsare thoroughly understood, the resultscan be extended to the design of thelogic gates and other more complexcircuits.
NMOS Inverter
-^
If
V I^ <V
NT
, the transistor is in
cutoff and
i^ D
=0, there is no
voltage drop across R
, andD
the output voltage isV
=o^
V DD
=V
DS
-^
If
V
I^
V^ NT,
the transistor is on
and initially is biased in saturation region
, since
V DS
V GS
-V
TN
.
-^
As the input voltage increases(V
GS
) , the drain to source
voltage (V
DS
) decreases and
the transistor inter into the non saturation region.
V
GS
=V
R
D
= V
DD
= V
DS
NMOS Inverter Transfer Characteristics with
load resister (Saturation Region)
V GS
=V
RD
= V
DD = V
DS
V
GS
=V
RD
= V
DD = V
DS
As the input is increased slightly abovethe
V
TN
,^ the transistor turns on and is in
the
saturation region
. The output
voltage is then v^ o
= V
DD
- i
RD
D^
where the drain current is given by i= KD^
(Vn
GS
- V
TN
= K
(Vn
- Vi
TN
By substituting the value of I
D^ from Eq.
16.7 we get , VO
= V
DD
- K
Rn
(VD
- VI
TN
which relates the output and inputvoltages as long as the transistor isbiased in the saturation region.
NMOS Inverter Transfer Characteristics with
load resister (transition Region)
•^
As the input voltage is further increasesand voltage drop across the R
becomeD^
sufficient to reduce the drain to sourcevoltage such that
V
DS
VGS
-V
TN
the Q-point of the transistor moves up theload line. At the transition point, we have^ v
ot^
= V
It^
- V
TN
where V
, and Vo^
, are the drain-to-sourceI
and gate-to-source voltages,respectively, at the transition point. Bysubstituting Equation (16.9) into (16.8),the input voltage at the transition pointcan be determined as, K
Rn
(VD
It^
- V
TN
2 ) + (V
- VIt
TN
) - V
DD
^0
V GS
=V
RD
= V
DD = V
DS
V
GS
=V
RD
= V
DD = V
DS
NMOS Inverter Transfer Characteristics with
load resister (Nonsaturation Region)
•^
As the input voltage becomesgreater than V
, the Q-pointIt
continues to move up the loadline, and the transistor becomesbiased in the nonsaturation region.The drain current is then iD^
= K
[2(Vn
GS
- V
TN
)V
DS
– V
DS
2 ]
= K
[2(vn
- VI
TN
)V
O^
–^
V
(^2) o
] (16.11)
The output voltage is then determined by
vo = V
DD
iRD
D Substitute the value of I
fromD
above equation we get the outputvoltage relation when thetransistor is biased innonsaturation region.
V
O^
V
DD
- K
Rn
[2(vD^
- Vl^
TN
)vo -
vo
2 ]
VGS
=V
RD
= V = DD
VDS
VGS
=V
RD
= V = DD
VDS
V^ GS
=V
RD
= V^ DD
= VDS
V^ GS
=V
RD
= V^ DD
= VDS
It should be be noted that the minimum output voltage, or the logic 0 level, for a highinput decreases with increasing load resistance, and the sharpness of the transitionregion between a low input and a high input increases with increasing load resistance.
Summary of NMOS inverter C-Vrelationship with the resister load
-^
Saturation region
-^
Transition region iD
= Kn(V
GS
- V
TN
(^2) ) = K
(Vn
- Vi
TN
(^2) )
V
O
= V
DD
- K
Rn
D
(V
- VI
TN
(^2) )
v
ot
= V
It
- V
TN
K
Rn
(VD
It^
- V
TN
(^2) _)
It^
- V
TN
) - V
DD
Nonsaturation region = K
[2(vn
- VI^
TN
)V
O^
V
(^2) o
]
iD
V
O^
=^
V
DD
- K
Rn
[2(vD^
- Vl^
TN
)vo -
v
(^2) o
]
VGS
=V
R^ D
= V^ DD
= V DS
VGS
=V
R^ D
= V^ DD
= V DS
NMOS Inverter with Enhancement
Load
-^
This basic inverterconsist of twoenhancement-onlyNMOS transistorsand is much morepractical than theresister loadedinverter, which isthousand of timeslarger than aMOSFET.
n-Channel MOSFET connected as
saturated load device
-^
An n-channel enhancement-modeMOSFET with the gate connected tothe drain can be used as load device inan NMOS inverter.
-^
Since the gate and drain of thetransistor are connected, we have VGS
=V
DS
When
V GS =V
>VDS
TN,
a non zero drain
current is induced in the transistor andthus the transistor operates insaturation only. And following conditionis satisfied. VDS
>(V
GS
-V TN )
VDS
(sat)= (V
DS -V
) becauseTN
VGS
=V
DS
or V
DS
(sat)= (V
GS -V
TN )
In the saturation region the drain current is i =KD^
(Vn GS -V TN
(^2) ) = K
(Vn DS -V TN
(^2) )
The i
D^
versus v
DS
characteristics are shown in Figure 16.7(b),
which indicates that this device acts as a nonlinear resistor
.
NMOS Inverter with Enhancement
Load/Saturated
In the saturation region the
load
drain current is iDL
=K
(VL
GSL
-V
TNL
= K
(VL
DSL
-V
TNL
For V
GSD
<V
TN
( driver transistor )
transistor is in cutoff mode and
does not conduct drain current 0= i
DL
=K
(VL
GSL
-V
TNL
= K
(VL
DSL
V^ TNL
V
GSL
=V
TNL
or V
DSL
=V
TNL
As a result the output high voltage
V^ O
is degraded by the threshold voltage
or
V
O,, max
= V
OH
=V
DD
-V
TNL
NMOS inverter with Enhancement
Load/Saturated (Cont.)
-^
As the V
=>VI
TND
A non zero drain current is induced in
the transistor and thus the drivetransistor operates in saturation only.As shown in the figure the followingcondition is satisfiedi
DD
=i
DL or
K
(VD
GSD
-V
TND
(^2) ) (^) = K
(VL
GSL
-V
TNL
(^2) )
Substituting V
GSD
=V
and VI^
GSL
=V
DD
-V
O
yields K
(VD
- VI
TND
(^2) ) (^) = K
(VL
DD
- V
O^
-^
V
TNL
(^2) )
Solving for V
O^
gives
V
= VO
DD
-V
TNL
-^
K
D
/K
(VL
-VI
TND
)
N-Channel Depletion-Mode
MOSFET
-^
In n- channeldepletion modeMOSFET, an n-channel region orinversion layer existsunder the gate oxidelayer even at zerogate voltage andhence term
depletion
mode.
-^
A negative voltagemust be applied to thegate to turn the device off.
-^
The
threshold
voltage
is always
negative
for this
kind of device.
NMOS Inverter with Depletion Load
(saturation condition)
With the gate and sourceare connected, V
GSL
Since the threshold voltageof load transistor isnegative, we haveV^ GSL
=0>V
TNL
= -(V
TNL
This implies that loadMOSFET is always
active
For an active device we canwriteV^ DSL
≥V
GSL
– V
TNL
= -V
TNL
=V
TNL
becauseV
GSL
NMOS Inverter with Depletion Load (cont.)
Case I:
when V
<VI
TND
(drive is
cutoff): No drain current conductin either transistor. That meansthe load transistor must be in thelinear region of the operation andthe output current can beexpressed as fellows
iDL
(linear)=K
[2(VL
GSL
- V
TNL
)V
DSL
V
DSL
2 ]
Since V
GSL
=0, and
iDL=
0=-K
[2VL
TNL
VDSL
+ V
DSL
2 ]
Which gives
V
DSL
=0 thus
V
= VO
DD
This is the advantage of the
depletion load inverter over theenhancement load inverter
NMOS Inverter with Depletion Load
(Cont.)
Case II:
When V
>VI
TND
(driver turns
on) and is biased in the saturation
region; however, the load isbiased in the nonsaturationregion. Under the condition we can write
iDD
=I
DDL
K^ D
(V
GSD
-V
TND
=K
[2(VL
GSL
- V
TNL
)V
DSL
- V
DSL
2 ]
Substituting V
GSD
=V
, VI
GSL
=0, and
V^ DSL
=V
DD
-V
O
Yields•
K^ D
(V
-VI
TND
=K
[2(-VL
TNL
)(V
DD
V^ O
)-V
DD
– V
)O^
2 ]
Which relates the input and output
voltage as long as the driver isbiased in saturation region and
Two transition points for NMOS depletion
load inverter
In the Figure the point B and C are
corresponding the two transition points:one for the load and one for the driver. The
transition point for the load
is given by,
VDSL
=V
DD
-V
Ot
Also V
DSL
=V
GSL
-V
TNL
By equating the relations we getVDD
-V
Ot
=V
GSL
-V
TNL
Since V
GSL
V0t
=V
DD
+V
TNL
As we know V
TNL
is negative. This implies that
Vot
<V
DD
The
transition point for the driver
is given
by VDSD
=V
GSD
-V
TND
Or in terms of input and output voltage we can
write VOt
=V
-VIt
TND
When both devices (driver and load) are in
saturation region
When both devices are biased in
saturation region the
Q point lies
between point B and C on the loadcurve,
and
KD
(V
GSD
-V
TND
= K
(VL
GSL
-V
TNL
Or √K
/KD
(VL
VI-^
TND
)=-V
TNL
Implies that input voltage is
constant as
the Q-point passes this region. If we further increased the input voltage,
the
drive is biased in the nosaturation region while load is in saturationregion. The Q-point moves between Cand D on the load curve. For theinput/output characteristics weequate two drain current equation KD
[2(V
GSD
- V
TND
)V
DSD
- V
DSD
2 ] = K
(VL
DSL
V^ TNL
Which becomesKD
/K
[2(VL
-VI
TND
)V
-VO^
2 ]=-(-Vo
TNL
Implies that input and output voltages are
not linear in this region.
VT Characteristics of NMOS Inverter with
Depletion Load
The Figure demonstrate in present configuration more abruptVTC transition region can be achieved even though the W/Lratio for the output MOSFET is small.
Transient Analysis of NMOS inverters
•^
The source ofcapacitance C
T
and C
T
are the transistor inputcapacitances andparasitic capacitancesdue to interconnect linesbetween the
inverter
stages.
-^
The constant currentover a wide range of VDSprovided by the depletionload implies that thistype of inverter switch acapacitive load morerapidly than the othertwo types inverterconfigurations.
The rate at
Transient Analysis of NMOS inverters (cont.)
-^
The fall time relativelyshort, because the loadcapacitor dischargesthrough the large drivertransistor.
-^
The raise time is longerbecause the loadcapacitor is charged bythe current through thesmaller load transistor.
(W/L)
=1L^
(W/L)
=4D^
F-0.5pF
16.2: NMOS Logic Circuit
NMOS logic circuits are constructed byconnecting driver transistor in
paralle
l,
series
or
series-parallel
combinations
to produce required output logic
function
NMOS NOR gate
-^
NMOS NOR gate can be constructed byconnecting an additional driver transistorin parallel with a depletion load inverter.
-^
The output of a NOR gate is only highwhen both inputs are at logic 0(low)i.e.
-^
If A=B=logic 0,
Then both driver transistors M
DA
and M
DB
are in cut off mode and
V
=V 0
DD
(logic 1)
For all other possible inputs V
= 0 (logic 0). 0
For example,If A=high (logic1) and B=low (logic0)Then M
DB
is in cut off mode and remaining
circuit behave as depletion load inverter.However, when both
driver transistors
are in active mode the value of the outputvoltage logic 0) is changed.
NMOS NOR gate: Special case when all
inputs are at logic 1
When A=B=logic 1Both driver transistors are switched into nonsaturation regionand load transistor is biased in saturation region. We have
iL=iD
DA +i DB
By substituting the values of current equation we can write as, K^ L (V GSL
-V
TNL
(^2) ) (^) = K
DA [2(V
GSA
- V
TNA
)V^ DSA
- V
DSA
2 ] + K
DB [2(V
GSB
-V
TNB
)V^ DSB
- V
DSB
2 ]
Suppose two driver transister are identical, which implies that, K^ DA
=K
=KDB
D
V^ TNA
=V TNB
=V
TND
As we know
VGSL
=
Also from figure
V GSA
=V
GSB
=V
DD
V^ DSA
=V
DSB
=V
0
By substituting all these parameters we can write above equation as, (-V
TNL
(^2) ) =^^2
(K D/K
L^ )[2(V
DD -V TND
)V 0 -V
(^2) O)
Conclusion:
The above equation suggested that when the both the driver are
in conducting mode
, the
effective aspect ratio
of the
NOR gate is
double.
This further suggested that output voltage
becomes slightly smaller when both inputs are high.
Because
higher the aspect ratio lower the output.
Concept of effective width to length ratios
For the NOR gate the effective width of the drivers transistors doubles. That means the effectiveaspect ratio is increased.
For the NAND gate the effective length of the driver transistors doubles. That means the effectiveaspect ratio is decreased
Parallel combination
Series combination
•^
At present, complementary MOS or CMOS has replaced NMOS at alllevel of integration, in both analog and digital applications.
-^
The basic reason of this replacement is that the power dissipation inCMOS logic circuits is much less than in NMOS circuits, which makesCMOS very attractive.
-^
Although the processing is more complicated for CMOS circuits thanfor NMOS circuits.
-^
However, the advantages of CMOS digital circuits over NMOS circuitsjustify their use.
CMOS: the most abundant devices on earth
Full rail-to-rail swing
high noise margins
z^
Logic levels not dependent upon the relative device sizes
transistors can be minimum size
ratio less
Always a path to V
dd
or GND in steady state
low
output impedance (output resistance in k
range)
large fan-out.
Extremely high input resistance (gate of MOS transistoris near perfect insulator)
nearly zero steady-state
input current
No direct path steady-state between power and ground^ ⇒
no static power dissipation
Propagation delay function of load capacitance andresistance of transistors
CMOS properties
16.3.1:p-Channel MOSFET
Revisited
-^
In p-channel enhancementdevice. A negative gate-to-source voltage must beapplied to create theinversion layer, or
channel
region
, of holes that,
“connect” the source anddrain regions.
-^
The
threshold voltage
V
TP
for p-channel enhancementload device is always
negative
and positive
for depletion-
mode PMOS.
-^
Cross-section of p-channel enhancement modeMOSFET
The operation of the p-channel is same as the n-channel device , except that thehole is the charge carrier, rather than the electron, and the conventional currentdirection and voltage polarities are reversed
Simplified cross section of a CMOS
inverter
-^
In the fabrication process, a separate p-well region isformed within the starting n-substrate.
-^
The n-channel MOSFET is fabricated in the p-well regionand p-channel MOSFET is fabricated in the n-substrate.
Different biasing conditions for a CMOS
inverter
.
-^
Case I: when NMOS is biased in
saturation
region
and PMOS is biased in
nonsaturation
region.
-^
The above condition can be achieved whenNMOS just start to conduct (V
=VI
TN
). Under
this condition we can write,
iDN
=i
DP
KN
[V
GSN
-V
TN
2 ]
=K
[2(VP
GSP
+V
TP
)V
SDP
-V
SDP
2 )]
In terms of input output voltage we can write,KN
[V
-VI
TN
2 ]
=K
P[
2(V
DD
-V
+VI
TP
)V
DD
-V
)-(VO
DD
-V
O
]
Transition points for PMOS and NMOS
As we know transition point for
the PMOS can be define as,
V
SDP
(sat)=V
SGP
+V
TP
OrV
OPt
=V
IPt
-V
TP
OrV
OPt
=V
IPt
+|V
TP
Similarly, the transition point
for NMOS can be written as
V
DSN
(sat)=V
GSN
-V
TN
orV
oNt
=V
INT
-V
TN
Biasing conditions for the CMOS
inverter (cont.)
•^
Case II: When both transistors are biased
in the saturation region. iDN
=i DP K^ N
[V
GSN
-V
TN
2 ]
=K
(VP^
GSP
+V
TP
In terms of input output voltage we
can write, K^ N
[V
-VI
TN
2 ]
=K
(VP^
DD
-V
+VI
TP
The input voltage can be determine
by simplifying above equation as, The above eq. can also be used to
determine input voltage at thetransition points.
N P
TN NP
TP DD It I
KK
V KK V V V V
=
1
Both are inSaturationregion
Symmetrical properties of the
CMOS inverter
CMOS inverter design consideration •^
The CMOS inverter usually design to have, (i)V
TN
=|V
TP
|
(ii) K
´n
(W/L)=K
´p
(W/L)
But K
´n
K
´p
(because
μ
n μ
)p
How equation (ii) can be satisfied?This can achieved if width of the PMOS is made two or
three times than that of the NMOS device. This isvery important in order to provide a
symmetrical
VTC
,^ results in wide noise margin.
CMOS inverter VTC
V
CC
V
CC
V
in
V
out
k
=kp
n kp
=5k
n
kp
=0.2k
n
k increasesp^ VTC moves to right
k
increasesn VTC moves to left
TH
= Vcc/
k = kn^
p
W
n^ ≈^
2W
p
Effects of V
It
adjustment
• Result from changing k
/kp
n
ratio:
– Inverter threshold V
It^
Vcc/
– Rise and fall delays unequal– Noise margins not equal
• Reasons for changing inverter threshold
– Want a faster delay for one type of transition
(rise/fall)
– Remove noise from input signal: increase one
noise margin at expense of the other
NMOS Transistor Capacitances: Triode
Region
C
ox ”^ = Gate-channel (^) capacitance per unitarea(F/m
C
GC
= Total gate channel (^) capacitance. C GS
= Gate-source (^) capacitance. C GD
= Gate-drain (^) capacitance. C GSO
and
C
GDO
= overlap
capacitances (F/m).
NMOS Transistor Capacitances:
Saturation Region
•^
Drain no longer connected tochannel
NMOS Transistor Capacitances: Cutoff
Region
-^
Conducting channelregion completely gone.
C
GB
= Gate-bulk capacitance
C
GBO
= gate-bulk
capacitance per unitwidth.
CMOS Inverter:
Switch Model of Dynamic Behavior
VDD
R
n
V
out
C
L
V
in^
= V
DD
V
DD
R
p
Vout
C
L
Vin
z
Gate response time is determined by the time to charge C
L
through R
p^
(discharge C
L^
through R
)n
CMOS inverter power
• Power has three components
– Static power: when input isn’t switching– Dynamic capacitive power: due to
charging and discharging of loadcapacitance
– Dynamic short-circuit power: direct
current from V
DD
to G
nd
when both
transistors are on
CMOS inverter static power
•^
Static power consumption:– Static current: in CMOS there is no static current
as long as V
in^
< V
TN
or V
in
V
DD
+V
TP
- Leakage current: determined by “off” transistor– Influenced by transistor width, supply voltage,
transistor threshold voltages
V
DD
V
<VI
TN
I^ leak,n
Vcc
V
DD
I^ leak,p
Vo(low)
V
DD
Dynamic Capacitive Power and energy stored in
the PMOS device
Case I: When the input is at logic 0
: Under this
condition the PMOS is conducting and NMOS is incutoff mode and the load capacitor must be chargedthrough the PMOS device. Power dissipation in the PMOS transistor is given by, P^ P
=i
VL
SDp
= i
(VL
DD
-V
)O
The current and output voltages are related by,i =CL^
dvL^
/dtO
Similarly the energy dissipation in the PMOS device can
be written as the output switches from low to high , Above equation showed the energy stored in the
capacitor C
when the output is high.L^ 2
2
2 0
0
0
0
0 0 12
) 0 2 ( ) 0
( , 2
,
)
( DD L P
DD L
DD DDL
P V O L VO DD L P
O
V
O L
V
O DD L P
O O DD L P P
V C E
V C
V V C E
C
V C E
d C d V C E dt ddt
V C P E
DD
DD
DD
DD
=
− − − = − =
−
=
−
= =^
∞ ∞
ν
ν
ν ν
ν
ν ν
Power Dissipation and Total Energy Stored
in the CMOS Device
Case II: when the input is high and out put is low: During switching all the energy stored in the load
capacitor is dissipated in the NMOS devicebecause NMOS is conducting and PMOS is incutoff mode. The energy dissipated in the NMOSinverter can be written as, The total energy dissipated during one switching
cycle is, The power dissipated in terms pf frquency can be
written as
2
1 2
DD L N^
V C E^
=
2
2
2
12
1 2
DD L DDL
DDL
N P T^
V C V C
V C E E E^
=
=
=
2 DD L
T
T
T^
V
fC
fE P
Et P
t P E^
This implied that the power dissipation in the CMOS inverter is directlyproportional to switching frequency and V
DD
2
Dynamic capacitive power
- Formula for dynamic power:• Observations
- Does not (directly) depend on device sizes– Does not depend on switching delay– Applies to general CMOS gate in which:
- Switched capacitances are lumped into C
L
- Output swings from Gnd to V
DD
- Input signal approximated as step function• Gate switches with frequency f
f
V C
P
DD
L
dyn
=
Dynamic short-circuit power
-^
Short-circuit current flows from V
DD
to Gnd
when both transistors are on saturation mode
-^
Plot on VTC curve: V CC
V
CC
V
in
V
out
I^ D
I^ max
I^ max
: depends on saturation currentof devices
Inverter power consumption
f
V C
Ptot
I V f t t I V f V C P
P
P
P
P
CC
L
leak CC
f
r
CC
CC
L
tot
stat
sc
dyn
tot
max
~
2
=
=
Power reduction
-^
Reducing dynamic capacitive power:– Lower the voltage!
- Quadratic effect on dynamic power
- Reduce capacitance
- Short interconnect lengths• Drive small gate load (small gates, small fan-out)
- Reduce frequency
- Lower clock frequency -• Lower signal activity
f
V C
P
DD
L
dyn
=
Summary of the noise margin of asymmetrical
CMOS inverter
NM
L^
= V
IL
- V
OLU
(noise margin for low input)
NMH = V
OHU
- V
IH
(noise margin for high input)
CMOS Logic Circuits
Large scale integrated CMOS logic
circuits such as watched, calculators,and microprocessors are constructed byusing basic CMOS NOR and NANDgates. Therefore, understanding ofthese basic gates is very important forthe designing of very large scaleintegrated (VLSI) logic circuits.
CMOS NOR gate
CMOS NOR gate can be
constructed by usingtwo parallel NMOSdevices and two seriesPMOS transistors asshown in the figure. Inthe CMOS NOR gatethe output is at logic 1when all inputs are low.For all other possibleinputs, output is low orat logic 0.
CMOS NAND gate
In CMOS NAND
gate the output isat logic 0 when allinputs are high.
For all other
possible inputs,output is high orat logic 1.
How can we design CMOS NOR
symmetrical gate?
•^
In order to obtained symmetricalswitching times for the high-to-lowand low-to-high output transitions,the
effective
conduction (design)
parameters of the
composite
PMOS and
composite
NMOS
device must be equal. For theCMOS NOR gate we can write as,
K
CN
=K
CP
By recalling effective channel width
and effective channel lengthconcept, the effective conductionparameter for NMOS and PMOSfor a CMOS NOR can be writtenas, Since K´
~2K´n^
p
p
p N
n
WL
K
WL
K
p
N^
WL
W^ L
=
2
2 2
N
P^
WL
WL
= ^
8
or
This implies that in order to get thesymmetrical switching properties , thewidth to length ratio of PMOS transistormust be approximately eight times thatof the NMOS device.
For asymmetrical case switching time is longer
Concept of effective width to length ratios
Parallel combination
Series combination
Fan-In and Fan-Out
• The Fan-in of a gate is the number of its
inputs. Thus a four input NOR gate has afan-In of 4.
• Similarly, Fan-Out is the maximum number
of similar gates that a gate can drive whileremaining within guaranteedspecifications.
Transmission Gates
• Use of transistors as
switches are called transmission gates
because
switches can transmitinformation from one circuitto another.
NMOS transmission gate as an
open switch.
-^
The figure shows NMOStransmission gate. Thetransistor in the gate canconduct current in eitherdirection.
The bias
applied to thetransistor determines which terminal acts as the drain
and which terminal
acts as the
source
.
When gate voltage
φ
=
The n-channel transistor is
cut off and the transistoracts as
an open switch
Characteristics of NMOS transmission gate (at high
input)
If
φ
=V
DD
, V
=VI
DD
, and initially, the output
V^0
is 0
and capacitance C
is fully discharged.L^
Under these conditions, the terminal ‘
a^ ‘acts as the
drain because its bias is VDD, and terminal ‘
b ’
acts as the source because its bias is 0. The gate to source voltage can be written as
VGS
=φ
- V
O^
or
VGS
VDD
-V
O
As C
charges up and Vo increases, the gate toL^ source voltage decreases. When the gate tosource voltage V
GS
become equal to threshold
voltage V
TN
, the capacitance stop charging and
current goes to zero. This implies that theV
=VO
(max) when VO
GS
=V
TN
Or V^ O
(max) = V
DD
-V
TN
d^
S G
This implies that output voltage never will be equal to V
DD
. ; rather it will be lower by V
TN
This is one of the disadvantage of an NMOS transmission gate when VI=high
Characteristics of NMOS
transmission gate (at low input)
•^
When V
=0 andI
φ
=V
DD
and V
=VO
DD
-V
TN
at t=o (initially).
It is to be noted that in the present case
terminal b acts as the drain and terminala acts as the source. Under these conditions the gate to source
voltage is,
VGS
=φ
-V
I
VGS
=V
DD -o
vGS=
v DD
This implies that value of V
GS
is constant.
In this case the capacitor is
fully
discharge to zero as the drain currentgoes to zero.
V =0O
This implies that the NMOS transistor
provide a “good” logic 0 when V
=lowI
VDD
-V
t
G S^
D
source
drain
gate
Why NMOS transmission gate does not remain in
a static condition?
•^
The reverse leakagecurrent due to reversebias between terminalb and ground beginsto discharge thecapacitor, and thecircuit does notremain in a staticcondition.
V
DD
-V
t
source
drain
gate
VO
(max) = V
DD
-V
TN
