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1
Bipolar Digital Circuits
(Chapter 17)
- There are two major classes of bipolar
digital logic circuits:
- Emitter Coupled Logic (ECL)• Transister-TransisterLogic (TTL)
ECL
is the fastest bipolar technology is used in
applications where high speed is required such ashigh speed circuits utilized in superconductors.A bipolar technology that has a higher noise margin isTTL. Transistors in this technology are drivenbetween cutoff and saturation.
The Current Switch
(Emitter-Coupled Pair)
emitter-coupled logic(ECL) is the currentswitch circuit whichconsists of matchedcomponents
3
Basic Concept of a Differential Amplifier
Circuit
-^
The emitter coupled logiccircuit (ECL) is based on thedifferential amplifier. Indigital applications , the diff-amp transistors are eithercutoff or in the active region.Saturation is avoiding in orderto minimize
switching times
and
propagation delay time
-^
For digital applications, theinput voltages are large,because one transistor isneeded to remain biased in itsactive region while theopposite transistor in cutoff.
T BE
T BE
v v S
C
v v S
C
e
I
I
e
I
I
/
2
/
1
1 2
=^ =
Differential Amplifier Circuit (cont.)
Case I: when Q
1 is on and Q
2
is
cutoff: This condition can be achieved ifv BE
of Q
is 120mV greater than 1
the
vBE
of Q
. Under this condition 2
the collector current of Q
is 100 1
times that of Q
Case II
:^ when Q1 is effectively
cutoff and Q2 is on: Again this condition can be achievedif
v^1
is less than
v^2
by at least
120mV.Under above two conditions the diff-amp operates as a current switch.Why?
5
The Current Switch
- Depending on how much higher or lower the
input voltage v
I^
is compared to V
REF
, the
reference current will switch to one of thelegs creating a voltage v
C
or v
C
6
Basic ECL Logic OR/NOR Gate
Case I:If both V
X^
and V
Y^
are less than
the reference voltage V
( atR
least 120 mV), then Q
1
and Q
2
are cut off and Q
R^
is in active
mode.This implies that;VO
>V
O
Case II: If either V
x^
or V
y^
become greater
than V
R^
then V
O
>V
O
The
OR logic
is
at the V
02
output
and
NOR logic is at the V
O
output An advantage ofECL is itscomplementaryoutputs
7
The ECL OR-NOR Gate
Three variations ofa 3-input ECL OR-NOR Gate
8
One Problem with the ECL circuit ?(the output voltage is not compatible with the input
voltage)
Normal operation of the circuit shown inthe figure, requiring that, basecollector junction must be reversebiased all the times but this is not alwayspossible. For example: In the ECL circuit shown in the Figure, If
either V
X^ or V
=VY
then Q
and Q 1
2 would turn on and the
collector voltage V
o^
would decrease
below V
+.
At this condition the base collector would then
become forward biased and transistorswitch into saturation region. Emitter followers ECL circuit has been design
to overcome this problem.
13
ECL Logic gate with reference circuit
- Power Dissipation The power dissipation of
standard ECL logiccircuit is given by,
-^
P
=(iD
Cxy
+i
CR
+i
+i 5
+i 1
+i 3
)(0 – V 4
Complete Two input ECL OR/NOR logiccircuit with reference voltage VR.
The reference circuit consist of resistors R
, R 1
2
and R
5,
diodes D
and D 1
and transistor Q 2
Example 17.
15
Propagation Delay Time
- The major advantage of ECL circuit is their
small propagation delay time.
- The change in voltage in ECL from logic 0 to
logic 1 is very small (0.7V), which means thatvoltage across the output capacitors do nothave to change up to V
DD
as changed in CMOS
circuits.
for the small propagation delay
time are higher power dissipation and smallernoise margins.
Is this a realistic fanout?
17
Voltage Transfer Characteristics(DC Analysis ref. example 17.3)
Case I
:^ NOR gate output (V
NOR
)
If input V
X^ and V
areY
a logic 0 or
-1.40V.Then Q1 and Q2 are cut off andV
NOR
=V
BE (on)= 0 - 0.7V = - 0.7V (logic
OR gate output (V
OR
)
Under the above condition, the Q
is on,R
and V
B = - 0.7V
and V
OR
= V
B -V
BE (on)= - 0.7- 0.7= - 1.40V
(logic 0) Case II: When V
=VX
=logic 1 orY^
V^ R
and Q 1
2 are
on and Q
is off, and VR
NOR
=-1.36V and
V^ OR
=-0.7V as shown in the figure.
Noise Margin
-^
As we know the noise marginsare defined as
•^
NM
=VL
IL
- V
OL
(noise margin for
low input)
-^
NM
=VH
OH
-V
IH
(noise margin for
high input)
-^
From given figure we have,
-^
VIL
= -1.17V and V
IH
= - 0.93V,
which are the point ofdiscontinuity in the VT curves. Similarly the high logic level isVOH
=- 0.7V and the low logic value is (^) VOL
= - 1.40V.
Using given data we have NM
=H
0.23V and NM
=0.23VL
The noise margins in ECL logic circuits are considerablylower than those for NMOS and CMOS.
19
Modified ECL Circuit Configurations:
Low power ECL
-^
In someapplications, bothcomplementaryoutputs may not berequired.
-^
If for example ORoutput is required,then we caneliminate resisterR
C
.
Analysis of modified ECL logic gate Case I: If V
=VX
=logic 1>VY
R
Under this condition Q
and Q 1
2 are
turn on and Q
R^ is off and logic 1
output voltage is: V
OR
=V
CC
Case II
: If V
=VX
=logic 0<Vy
R
Under this condition, transistors Q
and Q
2 are off and Q
R^ is on, then,
And the output voltage isVOR
=V
CC
CR
R^ C
CR
BE E
R
E^
i
R
on
V
V
I^
≅
−
=
) (
Problem: The logic 0 is not well define because R
E^
and R
C
may vary from
Problem: The logic 0 is not well define because ROne circuit to another during fabrication process.
E^
and R
C
may vary from
One circuit to another during fabrication process.
25
Is this a realistic fanout?
Voltage Transfer Characteristics(DC Analysis ref. example 17.3)
Case I
:^ NOR gate output (V
NOR
)
If input V
X^ and V
Y^ are
a logic 0 or
-1.40V.Then Q1 and Q2 are cut off andV
NOR
=V
BE (on)= 0 - 0.7V = - 0.7V (logic
OR gate output (V
OR
)
Under the above condition, the Q
is on,R
and V
B = - 0.7V
and V
OR = V
B -V
BE (on)= - 0.7- 0.7= - 1.40V
(logic 0) Case II: When V
=VX
=logic 1 orY^
V^ R
and Q 1
are 2
on and Q
R^ is off, and V
NOR
=-1.36V and
V^ OR
=-0.7V as shown in the figure.
27
Noise Margin
-^
As we know the noise marginsare defined as
•^
NM
=VL
IL
- V
OL
(noise margin for
low input)
-^
NM
=VH
OH
-V
IH
(noise margin for
high input)
-^
From given figure we have,
-^
V
IL = -1.17V and V
IH
= - 0.93V,
which are the point ofdiscontinuity in the VT curves. Similarly the high logic level isV OH
=- 0.7V and the low logic value is (^) VOL
= - 1.40V.
Using given data we have NM
=H
0.23V and NM
=0.23VL
The noise margins in ECL logic circuits are considerablylower than those for NMOS and CMOS.
Modified ECL Circuit Configurations:
Low power ECL
-^
In someapplications, bothcomplementaryoutputs may not berequired.
-^
If for example ORoutput is required,then we caneliminate resisterR
C
.
29
Analysis of modified ECL logic gate Case I: If V
=VX
=logic 1>VY
R
Under this condition Q
and Q 1
2 are
turn on and Q
R^ is off and logic 1
output voltage is: V
OR
=V
CC
Case II
: If V
=VX
=logic 0<Vy
R
Under this condition, transistors Q
and Q
2 are off and Q
R^ is on, then,
And the output voltage isV OR
=V
CC
CR
R^ C
CR
BE E
R
E^
i
R
on
V
V
I^
≅
−
=
) (
Problem: The logic 0 is not well define because R
E^
and R
C
may vary from
Problem: The logic 0 is not well define because ROne circuit to another during fabrication process.
E^
and R
C
may vary from
One circuit to another during fabrication process.
How can we establish a well define
logic 0 output?
-^
A well define logic 0 value canbe achieved by inserting aSchottky diode in parallel withresister R
.C
-^
When V
=VX
=0, QY
1
and Q
2
are
off and Q
R^
is on .Under this
condition the Schottky diodeis turn on and,
V
OR
= V
CC
-V
where
is turn on voltage of the
diode. Clearly V
OR
is
independent of any resister inthe circuit.
Also i
(max)= VR
/R
C
And i
=iD
-iE
(max)R
31
VOR
(Logic 1): when V
X^ and V
=logic 1Y
V
OR
(Logic 0): when V
and VX^
=logic 0Y
Power dissipationwhen output is logic 0
Power dissipationwhen output is logic 1
How the power dissipation is reduced?
If V
is the average ofR logic 1 and logic 0, thenoutput is compatible within input.
Diode transistor logic gate (DTL)
•^
The ECL circuits have very low noise margin (i. e. 0.23V). In order toovercome this problem, TTL circuits have been introduced.
-^
The basic building block of transistor transistor logic gate (TTL) isdiode transistor logic gate (DTL). Therefore, it is important to firstunderstand DTL.
37
Example 17.8 (cont.)
NAND gate : 0
Vx
vy
vo
Problem 17.10:
Using the results of example 17.8,calculate power dissipation for(a) V
= Vx
= 5V (b)Vy
= Vx
= 0.y
Solution (a) V
x^
= V
= 5 Vy
V
= V 1
BE
(sat) + 2
γV
= 0.8V + 2(0.7) = 2.2V
i^1
= (V
cc
-V
)/R 1
=(5-2.2)/4=0.7 mA 1
i^ RC
= (V
CC
- V
CE
sat)/R = (
0.1)/4 = 1.23 mAP=(i
RC
)V
CC
= (0.7V + 1.23)(5) = 9.65 mW
39
Transistor-Transistor Logic (TTL)
-^
In 1965,
TTL was introduced. Basically, the usage of
diodes in DTL was replaced with a transistor.
-^
The main improvement in TTL design over DTL isimproved switching speed due to reduction in thepropagation delay time. Pull down resister
DTL
TTL
Pull down resister R
B^ is no longer necessary, since The
excess minority carrier in the baser of Q
use Qo
as a path 1
to ground
TTL circuit with three emitter input
transistor
In Isoplanar integrated circuit technology, the number of inputs can be increaseby diffuse more emitters in the same base region as shown in the above figure. Thisapproach reduce the chip area required for the TTL IC.The above circuit perform same NAND gate operation as its DTL counterpart.
41
Analysis of TTL circuit: When at least one
or both inputs are low
-^
If either
or both inputs to Q1 are low
logic (0.1V), the base emitter junction willbecome forward biased. Under this condition, the collector currentof Q1 would be equal to the reveresaturation current
out of the base of Q
,o
and Q1 is biased in saturation and Qo incutoff. The base voltage of Q1 is V B
= V
X^
+ V
BE
(sat)
And the base current of Q
1 is
IB
= (V
CC
- V
B
) / R
1
And the collector voltage of Q
is 1
V
C
=V
CE
(sat)
V
=VO
CC
=Logic 1
NAND gate : 0
Analysis of TTL circuit: When all input are
high
•^
If all inputs are high, V
=VX
y=
5V.
•^
Under this bias condition, B-E junctionof Q1 are reverse biased and B-Cjunction are forward biased and Q1 isbiased in the
inverse active mode.
•^
The base voltage VB
is give by, 1
V
B
=^
V
BE
(sat)
Qo
+ V
BC
(on)
Q
If we assume that B-C and B-E junctions
turn on voltages are same then, i^ EX
= i
EY
β
iR B
and
i^ C
= i
B
EX
EY
= i
B
βR
i^ B
βR
)i B
V
(sat)=Logic 0=0.1VO
What would be relationshipbetween i
C
and
β R
, if number
of inputs are three
NAND gate : 0
0
1
1
0
1
0
1
1
1
1
0
43
Improved TTL NAND gate
The TTL NAND gate can be
improved by adding asecond current gain stageas shown in the figure. The characteristics of TTL
circuit will be discussed inthe followingexample(17.9)
TTL NAND gate: DC current –voltage analysis
NAND gate : 0
0
1
1
0
1
0
1
1
1
1
0
49
Draw back of the basic TTL NAND
gate
In all digital circuits there isalways existing a load capacitor,which is composed of the
input
capacitance of the load circuitsand the
capacitance of the
interconnect lines.During circuit operation this loadcapacitor must be charged throughcollector pull-up resistor.It has been estimated that theRC time constant of a basic TTLcircuit is about 60ns, which islarge enough compared to thepropagation delay time (PDT) of acommercial TTL circuit.
Addition of totem pole output stage to
overcome the problem
Case I
: How the output transistor discharge the load capacitor quickly? If Vx=Vy=1 Input transister Q1 is biased in the inverseactive mode, and both Q2 and Qo are driveninto saturation. The voltage at the base of Q
3
is,V^ B
=V
=VC^
BE (sat)
QO
+V
CE (sat)
Q
= 0.8 + 0.1 = 0.9V
Clearly,
V
B
is not enough to turn on Q
and 3
D
. 1 ⇒
Q
remain in cut off mode when output is 3
low.Under this condition the low output transistordischarge the load capacitor and pull theoutput low very quickly. That means PDTimproved.
Totem pole
V^ C
51
Addition of totem pole output stage to
overcome the problem (cont.)
-^
Case II:
How the output transistor
charge the load capacitor quickly? If V
=VX^
=logic 0Y
Under this biased mode Q
is on, and 1
Q
2
and Q
O^ are in cut off, and
V^ B
= V
CC=
5V, which is sufficient to turn on
Q3 and D ⇒
current in the output capacitor canflow through Q
and D 3
and 1
capacitance can be fully chargedquickly because the internalresistance of Q
and D 3
is very small 1
in conduction mode, so RC timeconstant
of the capacitor will be very
short. In other words, PDT of theTTL circuit has been improved.
Totem pole
Fanout
In digital circuits the main use of a logiccircuit is drive other similar type logicgates to perform a complex logicfunction. The maximum number ofsimilar type of logic gates that can beconnected to the logic gate outputwithout effecting proper circuitoperation is known as fanout.For a given value of
β
there is always
maximum allowable load current andload circuits.An another condition is the load currenti LL^
that Qo must sink from the load asshown in the figure. The above concept will be explored byfollowing example.
53
How can we estimate maximum fanout for the output
low condition?: Example 17.
54
How can we estimate maximum fanout for the output
low condition?: Example 17.10 (cont.)
55
How can we estimate maximum fanout for the output
low condition?: Example 17.10 (cont.)
56
Modified Totem-Pole Output stage
In modified TTL circuit a transistorQ
has been used instead of 4 diode. Advantages
of modified circuit:
i) the pair transistor Q
and Q 3
4
increase the fanout capability of theTTL gate in its high state ii) The output impedance is relatively
Lower in its high state , whichdecrease switching time. iii) The B-E junction of Q
3 behave as
diode D
and diode is no more need 1
to provide a voltage offset.
61
Problem17.24 (a)
Given that
β
=100,F
β
=0.2, FR
out
V
=Vx
=Vy
=0.1Vz
Determine i
B , i
B , i
B , i
C
and i
C
Sol:V
=VB
+Vx
BE
(sat)
Q
= 0.1 + 0.8 = 0.9V
i^ B
=i B
+(2-V
B
)/R
B
Where i
B
= [Vcc - V
EB (on)Q
] - V 3
B
/R
B
i^ B
=[{2 - 0.7} - 0.9]/1 = 0.4mA i^ B
=1.1 + 0.4 = 1.4mA i^ B
=0 because Q
2 is off
Since Q
3 is in saturation
i^ C
= 5iL’ for Vo high V
َََ B
=V
BC (on)Q
+ V
EB
(sat)Q
َ =0.8 + 0.7=1.5V^1
Ä
Q
is
off iَ^
B
= 2 - 1.5/1 = 0.5mA iَ^ L
=^
βR
iَ^ B
=0.2 X 0.5 = 0.1mA
i^ C
= 5x 0.1 = 0.5mA
Q
3 is cutoff!!
Schottky Transister-Transister Logic
(short storage time)
-^
The speed of the TTL circuits thus far studied is limited bytwo mechanism:
i)
All the transistors are in saturation mode while conducting,which limits the switching speed because the amount of timerequired to remove the storage charge from the base of thesaturated transistor is longer. The obvious solution of thisproblem is to use a BJTs in such a way that do not deepsaturate.
ii)
The resistances in the circuit, together with the varioustransistors and wiring capacitances, results relatively longertime constant which slow the
speed of TTL circuit. The
solution of this prblem is to reduced all resistances.
63
How can we prevent deep saturation?: By Using
a Schottky Clamped Transistor
•^
Schottky Clamped Transistor , transistorsare prevented from saturation byconnecting a Schottky diode between baseand collector. In BJT, saturation mode,can be avoided by limiting forward biasbase collector voltage, which is given by; V BC
(sat)=V
BE
(sat) - V
CE
(sat) = 0.8 - 0.2 =
0.6V
The Schottky diode limit the base current as
well as clamp the base collector voltage toturn on voltage (0.3-0.4V), which is lessthat the value required to saturate thetransistor. Hence, by using SchottkyClamped Transistor non saturation can beachieved, which exhibits a very short turnoff time.
Characteristics of Schottky Clamped Transistor
-^
Case I: When the transistor is inits active region, the basecollector junction is in reversebiased, which means thatSchottky diode is reverse bias andout of the circuit.
-^
Case II: when the transistor istrying to switch into saturationregion, the base collector junctionbecome forward biased. Underthis condition the base collectorvoltage become equal to diodeturn on voltage (0.3V), whichprevent the npn transistor deepinto saturation by shunting basecurrent through the diode.
65
Characteristics of Schottky Clamped
Transistor (cont.)
•^
From the figure we can write arelationship between differentcurrent in the circuit as,
-^
i^ C ´ =i
D^
C^
(i)
•^
i^ B = i
´ + iB^
D^
(ii)
•^
And
i^ C
βi
´B^
(iii)
•^
By combining (ii) and (iii) we canwrite as,
-^
i^ D
=i -iB^
´=iB^
-iB^
´/C^
β
•^
by substituting this value into (i)we can write as
-^
i^ C ´=i
´/C
β^
C^ or (^1) β
1
= ′^
C
B
C
i
i
i
1 β 1
= ′^
C
B
C
i
i
i
67
When the Schottky transistor is biased in
saturation mode
•^
Since the internal npn transistor is not in thedeep saturation mode, so we can assume thatVBE
=V
BE
(on) If the Schottky transistor is
biased in saturation then we can write,
-^
VCE
V
CE
(sat ) = V
BE
(on) - V
γ(SD)
•^
VCE(sat)
= 0.7 - 0.3 = 0.4V
•^
Although the output low logic is higher thanVCE
(sat) and results in slight reduced logic swing but disadvantage is quite minor incomparison with the speed improvement. When the Schottky transistor is at the edge of
saturation we can write, i^ D
i^ C
β
i^ B , and V
CE
= V
CE
(sat) = 0.1V
+V
CC
Problem
Given that
β
=10, V
BE
(on)=0.7V, V
γ(SD)=0.3V
(a) For no load i
=0, find iL
, iD
´, iB^
´C^
(b) Determine maximum load current that the transistor can sink and still
remain at the edge of saturation. Sol: (a):From the figure i
RC
=(V
CC
-V
CE
)/R
=(5-0.4)/2.25=2.04mAC^
i´= (2 + 2.04) / 1 + 1 / 10 = 3.67mAC^
i^ B ´= i
´/C^
β^
= 3.67 mA
i^ D
= i
´= 2 - 0.367 = 1.63mAB^
(b): Since transistor should be in the edge of saturation. This implies that
i^ D
i^ B ´= i
=2 mAB^
i^ C
βi
´ = (10)(2) = 20mA = iB^
RC
+i L
i^ =iL^
´-iC^
RC
18mA
′^
C B C
i i i
73
Role of different elements in ALSTTL
(cont.)
- Input section:The input diodes of the ALSTTL circuit
are replaced with emitter follower pnptransistor.
The emitter follower configuration
reduces load current by a factor ¼,and thus increases the fanout. Inaddition, the emitter base junction ofthe Q
compensates for additional 1
base emitter drop of Q
Role of different elements in ALSTTL
(cont.)
allows the
base of Q
to discharge
through Q
when the
output switches high tolow and provides morerapid discharging of theload capacitance.
75
Role of different elements in ALSTTL
(cont.)
-^
Output clamping diodes:
-^
The diode D
4
has been
added to the output andprovides the same functionas the input clamping diodeD
. That is, D 1
4
prevents the
output from overshootingground (when logic 1 switchto logic 0)by more than aturn on voltage (0.3V).
Operation of the
ALSTTL
circuit
-^
Case I: when V
=0.4VX^
Under this biased condition the E-B
junction of Q
is forward biased and in 1
active mode, and consequently the V
E
of
Q
is given by, 1
VE
= V
BE
= 0.4 + 0.7= 1.1 V
All the other transistor (Q
-Q 2
) are in cut 5
off mode (Why? )
Ä
VO
=high
Case II: When V
=3.6VX
The Q
1 is cutoff and Q
, Q 2
, and Q 3
5 turn
on, the V
E
is given by,
VE
= V
BE
(Q
)+V 2
BE
(Q
)+V 3
BE
(Q
VE
= 0.7(3) = 2.1 V
VO
=low
77
Problem 17.29a
Given that
=50, refer figure 17.
(a) Calculate power dissipation in the circuit
when the input is at logic zero.
(b) When the input is at logic 1Sol: For TTL circuit for low logic V
X^
= 0.4V
and for high logic V
=3.6Vx
V
E
= V
x^
+ V
BE
(Q
) = 0.4 + 0.7 = 1.1V 1
i^ E
= (V
CC
E
)/R
= (5-1.1)/40 = 0.0975mA. 1
This is the total current flowing throughthe circuit because all other transistors arein cutoff mode.
P = i
E
. V
CC
= (0.0975)(5) = 0.487mW
78
Problem 17.29b
b) When the input is at logic 1 b) :
V
E
= V
BE
(Q
)+V 2
BE
(Q
)+V 3
BE
(Q
)=(0.7)(3)=2.1V 5
i^ R
=(V
CC
-V
B
)/R
1
=(5-2.1)/40 =0.0725mA
VC
=V
CE
(Q
)+V 2
BE
(Q
)+V 3
BE
(Q
)=0.4+0.7+0.7=1.8V 5
I
R
=(V
CC
-V
C
)/R
=(5.1.8)/R 2
2
=0.065mA
V
C
= V
CE
(Q
)+V 3
BE
(Q
)=0.4+0.7=1.1V 5
I^ R
= (V
CC
-V
C
)/R
=(5-1.1)/1.5=0.26mA 3
P=V
CC
(I
R
+i
R
+i
R
)=1.98mW
79
Introduction of BiCMOS Digital Circuits
-^
BiCMOS is a VLSI technology that combines bipolar andCMOS devices into single integrated circuit.
-^
By combining the two technologies BiCMOS offers thefollowing advantage:
-^
i) Low power dissipation comparable to CMOS
-^
ii) Improved speed comparable to TTL or ECL technology
-^
iii) Large current driving capability comparable to TTL or ECL
-^
iv) large noise margin similar to TTL technology
Disadvantage:i)
Highest cost
ii)
Large fabrication cycle time up to thirty mask steps arecommon compared with ten to twenty for bipolar or CMOS.
80
BiCMOS Inverter (when input is low)
-^
Case I: When V
=logic 0I
The M
N^
and Q2 are off while Mp
conducts, which forces Q1 on. TheQ1 then provide a large outputcurrent to charge the loadcapacitance. The result is very shortlow-to-high propagation delay time.Q
1
is essentially acts as a pull up
transistor and
V
(max)=V 0
DD
-V
BE
(on),
because Q
turn off when Vo reaches 1
to this value, a disadvantage.
