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ECE 491 – Senior Design 1
Laboratory 5 – Asynchronous Serial Receiver
October 1, 2007
Goals
1. To develop an FPGA design of an Asynchronous Serial Receiver that converts serial
data from an RS-232 interface to parallel data one byte at a time.
2. To gain additional skill designing and debugging complex digital circuits using
Verilog and FPGAs.
Requirements
1. The receiver will include a clock input, a 1-bit serial data input rxd, an 8-bit data
output, a 1-bit rdy output, and a 1-bit ferr (“framing error”) output. As described
earlier, data will appear on the rxd input beginning with a single start bit and
ending with one or more stop bits.
2. The basic receiver circuit will operate at a clock rate that is 16 times the baud rate.
It will operate by sampling the rxd input and waiting for a falling edge that
signifies the beginning of a start bit. It will then wait until the middle of the start
bit and re-sample rxd to verify that the input is still low. If not, it must ignore this
“spurious start” and return to waiting for a falling edge. Otherwise, the circuit
must assert a low on the rdy output and wait until the middle of each of the
following successive bits and sample these inputs to assemble a parallel data
value. Finally, the circuit must sample the rxd input during the middle of the stop
bit to verify that the input is high. If not, a “framing error” has occurred and the
circuit will assert the ferr output until the next time a start bit is detected. The
rdy output will be asserted high when a full byte and stop bit have been
successfully received and held high until a new start bit has been received.
3. The receiver design must be parameterized so that it can be configured to operate
at different Baud rates (9600 baud default) given a 50Mhz clock input from the
Spartan 3 Starter Kit board. Instructions for configuring your circuit at different
baud rates must be included in header comment of your top-level Verilog file.
4. The receiver must be able to successfully receive two characters that have been
transmitted with only a single stop bit between the last bit of the first character
and the start bit of the second character.
Asynchronous Serial Rcvr.
RXD
DATA
RDY
FERR
CLOCK
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