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VHDL Lab Report: Designing a Synchronous 4-bit Serial Adder - Prof. Marcin Lukowiak, Lab Reports of Electrical and Electronics Engineering

The objectives, design process, and implementation details of a synchronous 4-bit serial adder using vhdl. Developing a vhdl entity declaration, implementing the adder structurally, and creating a testbench for verification. The testbench includes assert statements and a table with testing data.

Typology: Lab Reports

2009/2010

Uploaded on 03/28/2010

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EECC 0306- 351: Hardware Description Language Lab
-1-
LAB#4
The objectives of this lab exercise are:
1) To go through the design process of a synchronous circuit – 4-bit serial adder.
2) To test the model of a serial adder using a full test bench.
1)
a) Develop a VHDL entity declaration for the serial adder (all ports have to be std_logic and std_logic_vector
types).
Implementation details for a 4-bit serial adder entity
inputs: outputs:
in_a 4 bits
in_b 4 bits
control 2 bits (s1, s0)
clk 1 bit (100ns period)
reset_al 1 bit (asynchronous active low)
Sum 4 bits
carry 1 bit
b) Implement the serial adder in a structural way only. Your description is to be composed of 5 components and a
few internal signals (internal descriptions of all components are to be based on processes):
component describing 1 bit full_adder (introduces 8 ns delay),
component describing d - flip flop with enable and asynchronous reset (introduces 2 ns delay),
component describing 2 inputs and gate (introduces 4 ns delay), One of the inputs is to be active low the
second one active-high.
two components which describe 4-bit parallel load shift registers: regA and regB (introduce 20 ns
delay each). The functionality of the registers has to be exactly the same as 74LS194A – 4-Bit Bi-
directional Universal Shift Register - data sheet included. Implement registers using internal signals –
not bi-directional ports !
Registers and flip-flop are rising edge active !
Functional Details: On the rising edge of a clk signal when control is ”11”, the registers are loaded with in_a
(regA) and in_b (regB). On the rising edges of a clk when control is ”01”, the registers are shifted (LSB first)
into the 1 bit full adder.
The full adder’s sum bit is shifted into the register holding the in_a. After 4 rising edges on a clk while the control
remains ”01” the regA register contains the value in_a + in_b and carry should be the corresponding carry out bit.
The output sum is assumed not to be valid until 4th rising edge of a clk signal after load is set to ’0’.
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EECC 0306- 351: Hardware Description Language Lab

-1-

LAB#

The objectives of this lab exercise are:

1) To go through the design process of a synchronous circuit – 4-bit serial adder.

2) To test the model of a serial adder using a full test bench.

a) Develop a VHDL entity declaration for the serial adder (all ports have to be std_logic and std_logic_vector types).

Implementation details for a 4-bit serial adder entity

inputs: outputs:

in_a 4 bits in_b 4 bits control 2 bits (s1, s0) clk 1 bit (100ns period) reset_al 1 bit (asynchronous active low)

Sum 4 bits carry 1 bit

b) Implement the serial adder in a structural way only. Your description is to be composed of 5 components and a few internal signals (internal descriptions of all components are to be based on processes):

  • component describing 1 bit full_adder ( introduces 8 ns delay ) ,
  • component describing d - flip flop with enable and asynchronous reset ( introduces 2 ns delay ) ,
  • component describing 2 inputs and gate ( introduces 4 ns delay ) , One of the inputs is to be active low the second one active-high.
  • two components which describe 4-bit parallel load shift registers: regA and regB ( introduce 20 ns delay each ). The functionality of the registers has to be exactly the same as 74LS194A – 4-Bit Bi- directional Universal Shift Register - data sheet included. Implement registers using internal signals – not bi-directional ports!

Registers and flip-flop are rising edge active!

Functional Details: On the rising edge of a clk signal when control is ”11”, the registers are loaded with in_a ( regA ) and in_b (regB). On the rising edges of a clk when control is ”01”, the registers are shifted ( LSB first ) into the 1 bit full adder. The full adder’s sum bit is shifted into the register holding the in_a. After 4 rising edges on a clk while the control remains ”01” the regA register contains the value in_a + in_b and carry should be the corresponding carry out bit. The output sum is assumed not to be valid until 4th rising edge of a clk signal after load is set to ’0’.

EECC 0306- 351: Hardware Description Language Lab

-2-

The testbench will apply all inputs ( in_a, in_b, control, clk and reset_al ) and verify the outputs, using assert statements to flag errors.

Verification process will apply inputs ( in_a, in_b, control and reset_al ) and verify the outputs, using assert statements to flag errors. A constant (an array of a record type) will be used to store the values for in_a , in_b , sum and carry. The values to be used for in_a and in_b are:

in_a in_b sum carry X”0” X”4” X”C” X”E” X”8” X”A” X”F” X”F” X”F” X”1” X”A” X”5” X”2” ‘0’ X”8” X”7”

Please fill out the rest of the table and include it in your report (use ’hex’ notation). Do not change the result A+5 (see the 6 th^ row of the above table). I know that it is wrong. Your testbench checks the result and if any error occurs assert statement should give appropriate message. Timing is a crucial thing in your testbench. Remember to reset the circuit before you start a new addition. Explain why it is important.

Describe clk in a separate clock process, using simple signal assignment and wait for statements; clk starts with a falling edge at time 0 ns.

Report:

Please include the following items in addition to the standard lab report:

  • Describe your testing strategy,
  • Provide block diagrams of your serial adder and its testbench with ports and the names of the internal signals’ according to your code,
  • Include the table with testing data.

Questions:

  1. What are the dominant features for your VHDL code when modeling “Synchronous Logic” compared to “Combinational logic”?
  2. What’s the advantage to use “RECORD” data type in the Testbenchs?