EECC 0306- 351: Hardware Description Language Lab
-1-
LAB#4
The objectives of this lab exercise are:
1) To go through the design process of a synchronous circuit – 4-bit serial adder.
2) To test the model of a serial adder using a full test bench.
1)
a) Develop a VHDL entity declaration for the serial adder (all ports have to be std_logic and std_logic_vector
types).
Implementation details for a 4-bit serial adder entity
inputs: outputs:
in_a 4 bits
in_b 4 bits
control 2 bits (s1, s0)
clk 1 bit (100ns period)
reset_al 1 bit (asynchronous active low)
Sum 4 bits
carry 1 bit
b) Implement the serial adder in a structural way only. Your description is to be composed of 5 components and a
few internal signals (internal descriptions of all components are to be based on processes):
• component describing 1 bit full_adder (introduces 8 ns delay),
• component describing d - flip flop with enable and asynchronous reset (introduces 2 ns delay),
• component describing 2 inputs and gate (introduces 4 ns delay), One of the inputs is to be active low the
second one active-high.
• two components which describe 4-bit parallel load shift registers: regA and regB (introduce 20 ns
delay each). The functionality of the registers has to be exactly the same as 74LS194A – 4-Bit Bi-
directional Universal Shift Register - data sheet included. Implement registers using internal signals –
not bi-directional ports !
Registers and flip-flop are rising edge active !
Functional Details: On the rising edge of a clk signal when control is ”11”, the registers are loaded with in_a
(regA) and in_b (regB). On the rising edges of a clk when control is ”01”, the registers are shifted (LSB first)
into the 1 bit full adder.
The full adder’s sum bit is shifted into the register holding the in_a. After 4 rising edges on a clk while the control
remains ”01” the regA register contains the value in_a + in_b and carry should be the corresponding carry out bit.
The output sum is assumed not to be valid until 4th rising edge of a clk signal after load is set to ’0’.
