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The goals, requirements, and deliverables for laboratory 3 of the ece 491 course, focusing on gaining experience using the verilog simulator (modelsim) and creating self-checking testbenches for verilog modules. Students will develop testbenches for the generic counter and clock divider from lab 2, ensuring their proper operation through exhaustive simulation. The document also includes background information on verilog simulators and testbenches.
Typology: Lab Reports
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Laboratory 3 – Simulation and Testbenches September 17, 2007
Goals
Requirements
You will develop a self-checking testbenches for the following modules from Lab 2:
Deliverables
Background
In Labs 1 and 2, we compiled Verilog code directly into hardware and tested our designs in hardware. This approach works well for small designs, but becomes limited as designs become more complex designs. These designs are typically verified using a Verilog simulator. The Xilinx tools are designed to work with the Modelsim simulator, which is a product of Mentor graphics. To properly use a Verilog simulator, code must be added to the synthesizeable modules to generate input stimulus and check the output response of each module. This code is usually called a testbench or test fixture.
Testbenches are written using behavioral code – code that only works during simulation and that cannot be compiled into hardware. A typical testbench contains a Verilog "initial" block that contains a sequence of assignment statements combined with delay operators to apply a set of input vectors to the device under verification (DUV). Self-checking testbenches include code that tests the outputs of the DUV to check that they are correct. If not, they typically print error messages.
An example testbench was presented in class that verifies the correct operation of a BCD counter. In this lab, you will extend this testbench to verify the parameterized counter you designed in Lab 2. You will also use this testbench as a starting point for a testbench that verifies the operation of the Serial Transmission circuit designed in the next lab.
In the Lab