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Lecture notes on various types of flip-flops, including the r-s flip-flop and its issues with pulse mode circuits, the edge-triggered d flip-flop, and the process of building a jk flip-flop from a d flip-flop. Figure 1 illustrates a synthesized r-s flip-flop, figure 2 shows a two-stage solution to its pulse sensitivity issue, and figure 3 depicts an edge-triggered d flip-flop built from nand gates.
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Lab 5 Lecture Notes
1.0 R-S Flip-Flop
The R-S flip-flop can be synthesized from NAND gates. Figure 1 shows such a synthesized R-S flip- flop. Note that the output Y is "feed-back" to the lower NAND gate, and Y´ is "fed-back" to the upper NAND gate. This "feed-back" implementation can be problematic when used in pulse mode circuits, as the output may not have had time to stabilize before the input (S or R) goes away. Therefore, this circuit design is prone to pulse-width sensitivity.
Figure 1. R-S Flip-Flop
One solution to this problem is to build a second stage onto the R-S flip-flop, which does not latch the output until the input is removed. The design is presented in the lab for analysis and the circuit is shown in Figure 2, below.
Figure 2. Two-Stage R-S Flip-Flop
2.0 An edge-triggered D Flip-Flop
Figure 3 shows an example of D flip-flop built from "NAND" gates. The flip-flop that synchronizes the state changes during a clock pulse transition is the edge-triggered flip-flop. In this type of flip-flop, output transitions occur at a specific level of the clock pulse. When the pulse input level exceeds this threshold level, the inputs are locked out and the flip-flop is, therefore, unresponsive to further changes in inputs until the clock pulse returns to 0 and another pulse occurs. Some edge-triggered flip-flops cause a transition on the negative edge of the pulse.
Figure 3 consists of three basic latches. Nodes S' and R' must be maintained at logic-1 for the outputs (Q and Q’) to remain in their steady-state values. When S'=0 and R'=1, the output goes to the set state with Q=1.When S'=1 and R'=0, the output goes to the clear state with Q=0. Nodes S' and R' are determined from the states of the other two basic latches. These two basic latches respond to the external inputs D (data) and C (clock pulse).
Figure 3. D-type positive-edge-triggered flip-flop
3.0 Build a JK Flip-Flop from D Flip-Flop
Characteristic equation for D flip-flop is Q (t+1) = D
Characteristic equation for JK flip-flop is Q (t+1) = JQ’+ K’Q
So D = JQ’+ K’Q see figure 4.
Figure 4: JK Flip-Flop from D Flip-Flop