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Lab Assignment 2 for pMIPS Combinational Logic Blocks I | ECE 371, Assignments of Microprocessors

Purdue University GlobalMicroprocessors

Material Type: Assignment; Class: Microprocessor Systems; Subject: Electrical & Computer Engr; University: Purdue University-Calumet Campus; Term: Spring 2009;

Typology: Assignments

Pre 2010

Uploaded on 08/06/2009

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LABORATORY ASSIGNMENT # 2
pMIPS
Combinational Logic Blocks I
pMIPS
Combinational Logic Blocks I
Decoders, Multiplexers, and the Look-ahead Carry Unit (LCU)
SPRING 2009
ECE 371: Microprocessor Systems
Department of Electrical and Computer Engineering
School of Engineering, Mathematics, and Science
Purdue University – Calumet
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LABORATORY ASSIGNMENT # 2 pMIPS

Combinational Logic Blocks I

pMIPS

Combinational Logic Blocks I Decoders, Multiplexers, and the Look-ahead Carry Unit (LCU)

SPRING 2009

ECE 371: Microprocessor Systems Department of Electrical and Computer EngineeringSchool of Engineering, Mathematics, and Science

Purdue University – Calumet

The Look-ahead Carry Unit (LCU) • The carry look-ahead (CLA) approach isan alternative to the ripple-carry approach.• The CLA technique determines all^ intermediate carries at once.intermediate carries at once.^ – Hardware Parallelsim • The technique uses the concept of^ generating

and^ propagating

carries.

• When will a digit of addition carry?^ – Either when the addition

generates

or^ the

next less significant bit carries

and^ the

addition

propagates

The LCU:

g & p: So What?

c^ = g

+ c^ ·p

= x^ ·y

+ c^ ·^ (x

+ y^ )

– cisI+^

only^ a function of

x, y,^ ii

and^ ci

ci+1 • Available instantly (not big delay like ripple carry).• Space complexity large due to parallelism – Equation can get big! => Hardware gets big! – ccircuits can be realized as 2-level Sum ofI+1 Product (SOP) (2 levels of gate delay)

= g+ c i^

·p= xii^

·y+ cii^

·^ (x+ yii^

)i

The LCU: Higher Order G’s & P’s •^ The LCU logic can be used in higher-leveldesigns by having each CLA logic circuitproduce a propagate and generate signal to ahigher-level CLA logic circuit. •^ Group

- Propagate

( P ) and

Group

- Generate

( G )

conditions can be deduced for 4

- bit CLA logic

•^ Group

- Propagate

( P ) and

Group

- Generate

( G )

conditions can be deduced for 4

- bit CLA logic

chunks.^ G= g^0

+ g·p 3 2

+ g·p 3 1

·p+ g 32

·p·p 032

·p^1

P= p^0

·p·p 012

·p^3^ c^4

= G + Pc

The 4-bit LCU Module

Hierarchical Multiplexers^ A 4-to-1 Multiplexer Example

Hierarchical Binary Decoders^ A 3-to-8 Binary Decoder Example^ w^0^ w^2

y^0 y^1 y^2 y
w^ y^00 wy^1 1^ y^2^ y En
w^1 w^2
y^3
yEn^3 wy 00 wy 1 1 y^2 y En^3
y^4 y^5 y^6 y^7
En

VHDL

GENERIC

Statement

•^ Allow for reusable VHDL designs•^ Can create parameterized modules•^ Can pass “information” to design modules•^ What can be parameterized?^ •^ Bit-widths of hardware units•^ Bit-width/depth of memories (ROMs, RAMs, CAMs)^ •^ Delay information of hardware units (simulation only)•^ Delay information of hardware units (simulation only)^ •^ Others •^ Other languages that compare^ •^ C++ (templates), Java (generics), Verilog (parameters) •^ Syntax

ENTITY <entity_name>

IS GENERIC

( generic declarations … ); PORT ( port declarations … ); END ENTITY

<entity_name>;

VHDL

IF-GENERATE

Statement

•^ Allows for the design of “conditional” hardware•^ Is a concurrent statement…order doesn’t matter•^ The “label” is not optional•^ Powerful when utilized with

GENERICs

•^ Can be nested•^ Does not have

ELSE^ part.

•^ If^ ELSE

required, use independent

IF-GENERATES

•^ If^ ELSE

required, use independent

IF-GENERATES

•^ Syntax

label :

IF (Boolean expression)

GENERATE

--concurrent (dataflow) statements--component instantiations--for-generate statements--if-generate statements--selected/conditional assignments END GENERATE

label;

VHDL

GENERIC/FOR-GENERATE Example 1: Dataflow Modeling

LIBRARY

IEEE; USE^ IEEE.STD_LOGIC_1164.

ALL ;

ENTITY andGate_nbit

IS GENERIC

( N :^ POSITIVE

:= 4 );

PORT ( A, B

:^ IN STD_LOGIC_VECTOR

(N-1^ DOWNTO

0);

F^ :^ OUT^ STD_LOGIC_VECTOR

(N-^1 DOWNTO

  1. );

F^ :^ OUT^ STD_LOGIC_VECTOR

(N-^1 DOWNTO

  1. );

END ENTITY

andGate_nbit; ARCHITECTURE

dataflow

OF^ andGate_nbit

IS

BEGIN^ The_AND_Gates :^ FOR

index IN^^0 TO^ N- GENERATE

F(index) <= A(index)

AND^ B(index);

END GENERATE

The_AND_Gates; END ARCHITECTURE

dataflow;

VHDL

GENERICs

Example 3: Instantiating Generic Components ARCHITECTURE^ structure

OF^ andGate_nbit

IS

COMPONENT

andGate_nbit

IS GENERIC ( N :

POSITIVE

:= 4 ); PORT ( A, B

:^ IN^ STD_LOGIC_VECTOR

(N-1^ DOWNTO

0);

F^ :^ OUT STD_LOGIC_VECTOR

(N-1^ DOWNTO

  1. );

END COMPONENT

andGate_nbit; --declare a constant named TWELVE with a value of 12 CONSTANT^

TWELVE :^

POSITIVE^

:= 12;

SIGNAL^ Q, R, S :

STD_LOGIC_VECTOR

(3^ DOWNTO

0);

SIGNAL^ Q, R, S :

STD_LOGIC_VECTOR

(3^ DOWNTO

0);

SIGNAL^ X, Y, Z :

STD_LOGIC_VECTOR

(11^ DOWNTO

0);

BEGIN^ ----------------------------------------------------------------------------^ --since this is a 4-bit AND gate and the default value for parameter N is 4,--a GENERIC MAP is not required.

However, IT IS HIGHLY RECOMMENDED!

---------------------------------------------------------------------------- AND_Gate_4bits : andGate_nbit

PORT MAP

( A => Q, B => R, F => S );

------------------------------------------------------------------------------since this is a 12-bit AND gate and the default value for parameter N is 4,--a GENERIC MAP is required. must provide N with a value of 12----------------------------------------------------------------------------- AND_Gate_12bits : andGate_nbit

GENERIC MAP

( N => TWELVE )

PORT MAP (A => X, B => Y, F=>Z ); END ARCHITECTURE

structure;

VHDL

GENERIC/GENERATEs

Example 4: N-bit Adder from HAs & FAs

ENTITY^
rca_nbit
IS
GENERIC
( N :^ POSITIVE
PORT(^ X, Y :
IN^ STD_LOGIC_VECTOR
(N-1^ DOWNTO
Sum^ :^
OUT STD_LOGIC_VECTOR
(N-1^ DOWNTO
Cout :^
OUT STD_LOGIC
END ENTITY
rca_nbit;
ARCHITECTURE
structure
OF^ rca_nbit
IS
COMPONENT
halfAdder
IS
PORT ( A, B
IN^ STD_LOGIC
Cout, Sum :
OUT STD_LOGIC
END COMPONENT
halfAdder;
COMPONENT
fullAdder
IS
PORT ( A, B, Cin :
IN^ STD_LOGIC
Cout, Sum :
OUT STD_LOGIC
END COMPONENT
fullAdder;
SIGNAL^
carries :
STD_LOGIC_VECTOR
(0^ TO^ N-1);
BEGIN