Laboratory Five
Design of a One-of–Four Multiplexer Module
References
Mentor On-Line Help Manual
Mentor Tutorials posted on the ECE 4500/5950 Class Web Page
Objectives
1. Design a combinational logic circuit module using dynamic np-CMOS technology.
2. Study the properties of dynamic combinational logic circuits
Specifications
You should develop a concise layout of a circuit module that implements a One-of-Four
Multiplexer circuit. The circuit inputs are as follows: I0 – I3 (four data inputs), SEL0, SEL1 (two
select inputs, SEL0 is LSB). The circuit output is Y. The function of the circuit is to pass the
level of the signal at the selected input port to the output port.
Your design should be based upon dynamic np-CMOS logic. Only un-complemented input
signals are available. The terminal configuration of the layout should allow access to all signals
from both top and bottom of the cell. The power lines should be on first-layer metal rails that
pass completely through the cell in a horizontal direction. Be as generous as you can with the
widths of the power lines so that their current-carrying capacities will be reasonably high. The
minimum feature sizes for L and W are 1.2µm and 2.0µm, respectively.
Tasks
1. Capture the schematic diagram of your MUX using Design Architect. Name your file like
xxx_lab5.
2. Design a suitable functional simulation for the circuit using Eldo and Xelga.
Verify the logic function for the circuit on the basis of your simulation results.
3. Use Eldo and Xelga for transient analysis.
From transient analysis, obtain tPHL, tPLH, and tP, as well as the minimum and maximum clock
frequencies, respectively. A 50% duty cycle clock signal should be used for transient analysis.
4. Create a layout for the circuit.
5. Perform parasitic extraction.
Lab Report (hard copy) should include:
a) Discussion of your design (a transistor-level schematic diagram is included).
b) Printout of the schematic diagram.
c) Printout of the layout.
d) Printouts of the functional simulation using Eldo and Xelga.
e) Printouts of the transient simulations.
f) Final specs of your circuit (delay times tPLH and tPHL, the average
delay tP, fCLK, min and fCLK, max, and the size of the actual layout area).
