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Lab 2: Measuring Electrical and Physical Parameters of MOS Devices
EECS 312 Winter 2009
Due: 3 February
Introduction
In this lab, you will be studying the I-V characteristics of MOS devices. In the first part, you will generate multiple plots from which you will extract various device parameters, such as VT 0 , k’ , and λ. You will then re-simulate with a body bias to measure γ. In the next portion of the lab, you will directly measure the gain factor k, VT 0 , VT , and γ using a circuit that keeps the transistor in the saturation region. Please keep in mind that the parameters you extract from the plots may not necessarily agree with the nominal text book values, but should be similar.
Getting Started
Before you begin, you should create a new directory, e.g., lab2 to hold all schematics for this lab. You should open Cadence from within the lab2 directory to ensure all your schematics get saved to this location.
Part 1: MOS ID v VDS
In this part, you will be creating a simple circuit that you will use to simulate and measure physical and electrical parameters of the MOS device. You may use any method you feel comfortable with, including those presented in lecture and used in homework. The MOS models are Spice level 53 in 0.25 micron technology. In this part you will learn how to extract some basic device parameters and find how well they correlate with the simple first-order model presented in the text. Known Parameter NMOS PMOS VDSAT 0.63 V -1.0 V Substrate Doping (^) NA = 2.35 × 1017 cm-3^ ND=4.16 × 1017 cm- Leff 0.20 micron 0.20 micron 1.1 Schematic The schematic is shown in Figure 1 for measuring NMOS device parameters. Figure 2 shows a similar schematic for the PMOS device. You will want to name the voltage sources as shown in Figure 1. This can be done by going into the properties (hit ‘q’) and then change the instance name to the desired name. The schematic in Figure 1 will allow us to easily control VDS , VGS, and VBS. For VDS, enter the the DC Voltage as VDS, for
VGS, enter the DC voltage as VGS and for now VBS =0V for NMOS. NOTE: For the N_Transistor, use nmos4 and for P_Transistor, use pmos Figure 1 : Schematic for the NMOS Circuit Figure 2 : Schematic for the PMOS Circuit
Exercise #2: Find the same device parameters, VT 0p, kp’ , and λ p. Is the device working in the velocity saturation region at all? Compare these plots to those from the NMOS device. About how much stronger is the NMOS device compared to the PMOS? Please hand in a plot of your curves that resembles Figure 4 (with data points labeled).
- Exit the waveform viewer, close the current schematic, and create a new schematic for the PMOS device as shown in Figure 2. For the PMOS, the source is now the top terminal the drain is located on the bottom (opposite of the NMOS). Please notice the different names for the voltage sources. Also, in this circuit the substrate must always be biased such that it is equal to or greater than the source potential. For this exercise, set VSB to 0. Repeat the steps above to get an Ids Vs Vds curve for PMOS, which should be similar to Figure 4. Figure 3 : ID – VDS for NMOS with VGS = [0.5,1.0,1.5,2.0,2.5]V and VBS=
Exercise #3: Find the body effect coefficient of the NMOSFET by using data values from when VBS=0V and when VBS= -1V. Please hand in a plot similar to Figure 3, but now with the body bias applied and all data points labeled. Figure 4 : ID – VSD for PMOS with VGS = -[0.5,1.0,1.5,2.0,2.5]V and VBS= 1.3 Finding γ with VBS ≠ 0 In this part, you will re-simulate the same circuit to generate a new family of curves with a body bias applied. From the plots generated, you will be able to determine the body- effect coefficient γ.
- If you are still in simulation mode, close the ADE and return to the original NMOS schematic (Figure 1).
- Change the voltage source VBS to - 1V.
- Run the simulation again as described above.
- Generate a new family of ID-VDS curves with cursors located at the same location as in the previous NMOS simulation. Please print the resulting plot and label accordingly.
- Repeat above steps for the PMOS schematic now.
The circuit configuration that will allow the device to remain in saturation is given in Figures 5 and 6, corresponding to NMOS and PMOS, respectively. In these circuits, VD is shorted to VG such that VDS = VGS and therefore VDS > VGS - VT0 for all VGS , ensuring that the device remains in saturation mode (Of course one has to make sure that device is not working in velocity saturation region ). Both k and VT0 can be directly measured by plotting € 2 ID vs VGS to find the slope and x -intercept of the resulting line with no body bias applied.
The body-effect coefficient (γ ) and 2φ f can also be measured by then applying body bias
to find how the threshold voltage has changed. By then comparing this to the case with
no body bias ( VT0 ), you will be able to solve for γ and 2 φ f.
3.1 Schematic The new schematics you will be creating are shown in Figures 5 and 6. Figure 5 : Schematic for NMOS
Figure 6 : Schematic for PMOS 3.2 Simulation
- If you are still in simulation mode from previous simulations, exit and close all open schematics. Create the schematics for the NMOS and PMOS circuits given in Figures 5 and 6 In the PMOS circuit shown, the substrate must always be biased such that it is equal to or greater than the source potential.
- Open the NMOS schematic and for VBS, enter the the DC Voltage as VBS and for VGS, enter the DC voltage as VGS. Open the ADE.
- Choose DC as your analysis type. Under DC Sweep Analysis , hit Select Source and click the voltage source VGS on the schematic. Enter From 0V To 2.5V By 0.1V and click OK.
- Click on Variables > Copy From Cellview and enter the default value of 2.5V for VGS and 0V for VBS
- To get the Ids vs Vgs curve, click on Outputs >To be Plotted > Select on Schematic and select the Drain Terminal of the NMOS on the schematic. NOTE : You need to select the square red terminal on the NMOS to get the current at that node. If you select a wire, it will give you the voltage at that node.
- The selected terminal name will appear in the ADE under Outputs. Double-click
LAB REPORT
Complete Exercises #1-5, and make sure all plots are labeled with titles indicating what exercise it is for, and whether it is for the NMOS or PMOS device. All work and answers must be on a separate piece of paper. If Matlab, Python, R, or Excel is used, you must also supply a copy of your script used to help solve that part of the problem. Exercise #5: Calculate kn , kp , VT0n , VT0p , γ (^) n , γ (^) p , 2 φ fn , and 2 φ fp using the plots generated in Section 3.2. Please indicate which values you are using from the graph to calculate these parameters. How do these values differ from Exercises #1‒#4?
